The disclosure describes an implementation of a combinational thermometric-R2R that includes a thermometric DAC circuit to output the coarse output steps, an R2R circuit to control the fine output steps, and a resistor in series with the thermometric and R2R circuits. The techniques of this disclosure implement a fine resolution DAC, on the order of two nanoamps per bit, that operates at low current, yet maintains monotonicity throughout the DAC output range.

A semiconductor device includes first and second terminals, a reference resister being coupled between the first and second terminals, third and fourth terminals, a sensor resister being coupled between the third and fourth terminals, a first buffer which supplies a first reference voltage to the first terminal, a second buffer which supplies a second reference voltage to the fourth terminal, a reference voltage generation circuit which supplies one of first and second voltages alternately in a time division manner as the first reference voltage and supplies the other as the second reference voltage, a first analog-to-digital conversion circuit which performs analog-to-digital conversion on a signal line coupled to the third terminal, an RC filter disposed on the signal line, a noise detector which detects noise of the signal line, wherein a time constant of the RC filter is changed based on a result of the noise detector.

A digital-to-analog conversion circuit, comprising: an R−2R resistive network (10) configured to be connected between an output end and a ground end; an output voltage selection unit (20) configured to be connected between the output end of the R−2R resistive network (10) and a voltage output terminal; an output voltage trimming unit (30), wherein the output voltage trimming unit (30) is provided between a 2R resistor on at least one branch of the R−2R resistive network (10) and the ground end.

Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

An analog-to-digital converter (ADC) and an operation method thereof are provided. The ADC includes: a comparator which compares a signal input through a first input terminal and a signal input through a second input terminal, and outputs an output value according to the comparison result. A successive approximation register receives the output value of the comparator, sets digital signal values from a most significant bit to a least significant bit, and outputs the digital signal values. A digital-to-analog converter receives the digital signal values, and converts it into an analog signal based on a reference voltage Vref, and outputs it to the second input terminal. A noise component is added to the input signal and to the analog signal Vdac′.

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

A semiconductor device includes first and second terminals, a reference resister being coupled between the first and second terminals, third and fourth terminals, a sensor resister being coupled between the third and fourth terminals, a first buffer which supplies a first reference voltage to the first terminal, a second buffer which supplies a second reference voltage to the fourth terminal, a reference voltage generation circuit which supplies one of first and second voltages alternately in a time division manner as the first reference voltage and supplies the other as the second reference voltage, a first analog-to-digital conversion circuit which performs analog-to-digital conversion on a signal line coupled to the third terminal, an RC filter disposed on the signal line, a noise detector which detects noise of the signal line, wherein a time constant of the RC filter is changed based on a result of the noise detector.

An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.