A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

Systems, apparatuses and methods may provide for technology that conducts, by a differential signal path, signed multiply-accumulate (MAC) operations on first analog signals and multibit weight data stored in the differential signal path, and outputs, by the differential signal path, second analog signals based on the signed MAC operations.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.