A method of an electronic device includes: providing a capacitive digital-to-analog converter having a reference voltage input; providing a reference voltage providing circuit to generate a reference voltage to the reference voltage input of the capacitive digital-to-analog converter; and, generating a compensation signal into the reference voltage input of the capacitive digital-to-analog converter in response to at least one switching of at least one capacitor in a switchable capacitor network of the capacitive digital-to-analog converter.

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

Noise sources in a pipelined ADC circuit can include kT/C sampling noise from a capacitor DAC circuit and residue amplifier sampling noise. The kT/C sampling noise is inversely proportional to the size of the sampling capacitors; the larger sampling capacitors produce less noise. However, larger sampling capacitor can be difficult to drive and physically occupy significant die area. By using the described techniques, the inversely proportional relationship between the sampling noise and the size of the sampling capacitors is no longer true. The size of the sampling capacitors can be greats reduced, which can reduce the die area and reduce the power consumption of the ADC, and the kT/C sampling noise can be canceled using correlated double sampling (CDS) techniques.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Disclosed are circuits and methods for a CDAC with capacitive references. Individual reference capacitors can be implemented to provide the reference voltages for each input capacitor in a CDAC. For example, each input capacitor may be allocated a high-reference capacitor and a low-reference capacitor to provide the reference voltage to the respective input capacitor. Each of these reference capacitors is charged along with the input capacitor when the CDAC is configured into a loading configuration, and then used to convert digital data to an analog signal when the CDAC is configured into a conversion configuration. Accordingly, the reference voltage for each input capacitor is provided by a separate power source. This contrasts with current solutions in which the reference voltages for the input capacitors are provided by either a singular high-reference voltage source or low-reference voltage source.

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

An interdigital capacitor and a multiplying digital-to-analog conversion circuit, where the interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy finger metal.