Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

An amplifier for headphones including a current digital-to-analog converter (DAC) configured to output a current based on a digital audio input signal, an output electrically connected to a speaker and configured to output an output signal to the speaker, and a pulse width modulation (PWM) loop configured to receive an error signal, the error signal based on a difference between the current from the current DAC and a current of the output signal, and generate the output signal based on the error signal. The PWM loop includes an analog-to-digital converter (ADC) configured to receive an analog signal based on the current from the current DAC and output a digital signal representing the analog signal, and an encoder configured to receive the digital signal and output a pulse having a width based on the analog signal.

A pulse width modulation (PWM) digital-to-analog conversion circuit includes switches 102, 104, 114, 116 controlled by a first PWM signal, and switches 106, 108, 110, 112 controlled by a second PWM signal. A first operational amplifier (op-amp) includes a first input coupled to an output of a filter, and a second input coupled to an output of the first op-amp. During a first time period, an output of a second op-amp is coupled to an input of the filter via switches 102 and 104, and an output of a third op-amp is coupled to the output of the first op-amp via switches 114 and 116. During a second time period, the output of the second op-amp is coupled to the output of the first op-amp via switches 106 and 108, and an output of the third op-amp is coupled to the input of the filter via switches 110 and 112.

A system may include an output stage for driving a load at an output of the output stage, a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation, a linear mode path configured to pre-drive the output stage in a second mode of operation and a loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path. The pulse-width modulation mode path and the linear mode path may be configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that allow an improvement in the rate of modulation of PWM signals. Pulse width modulation (PWM) is performed to convert one of a 0 or 1 represented by a bit of a pulse density modulation (PDM) signal into which an audio signal has been PDM-modulated, into a maximum-length pulse of a maximum pulse width of a PWM signal having a period equal to the period of the PDM signal, and convert the other of the 0 or 1 of the PDM signal into a minimum-length pulse of a minimum pulse width of the PWM signal at a position adjacent to the center of the period of the PWM signal. The present technology is applicable, for example, to audio reproduction systems that reproduce audio signals.