Embodiments relate to a light-emitting-diode (LED) cell that includes a LED and a controller. The controller receives a brightness data signal and generates a driving signal corresponding to the brightness data signal. The controller includes a comparator that receives the brightness data signal and a control waveform signal. The controller is coupled to a switched current source that generates a driving current based on the driving signal.

A pulse density modulator encodes an electrical parameter of an external element into a data stream signal. The electrical parameter has a property which causes a predetermined error in the data stream signal. The pulse density modulator includes a digital to analog converter having a sensor element connectable to the external element, and an adjuster circuit adapted to adjust an output of the digital to analog converter based on the data stream signal to correct the predetermined error in the data stream signal. A corresponding method of correcting a data stream signal of a pulse density modulator is also presented.

A digitally compensated hysteretic power supply with enhanced resolution is provided. Such a power supply includes a comparator that is used to compare a load current sense signal with an internal signal generated from a digital-to-analog converter (DAC). A compensation circuit at a DAC input operates to improve current accuracy beyond the given DAC resolution. The current sense signal is converted to its digital equivalent, which is fed to a proportional-integral (PI) compensation loop, which in turn generates a relatively precise high resolution DAC input value. The DAC uses the higher part of the DAC value. The lower part of the DAC value is treated as a duty cycle number, and the DAC output is toggled between two levels at this duty cycle. This toggling generates a current output signal having a value that is the average of the two toggled values.

In an example, an apparatus includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input coupled to the first digital output. The apparatus also includes a multiplexer having a multiplexer output and first and second multiplexer inputs, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/f.sub.s; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N1)/f.sub.s, and by a delay of 1/f.sub.s. The positive sub-DAC and the negative sub-DAC start the conversion at the same time. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of f.sub.s.

This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (P.sub.Width) and to output a PWM signal (S.sub.PWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.

A method for approximating a first signal having a first oscillation period within a quantized time interval using a second signal is provided. The second signal has a second oscillation period. The method includes calculating a phase offset of the first signal at at least one position within the quantized time interval. Further, the method comprises shifting the second signal within the quantized time interval until a phase offset of the second signal at the at least one position satisfies a quality criterion related to the phase offset of the first signal.

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.