A method for approximating a first signal having a first oscillation period within a quantized time interval using a second signal is provided. The second signal has a second oscillation period. The method includes calculating a phase offset of the first signal at at least one position within the quantized time interval. Further, the method comprises shifting the second signal within the quantized time interval until a phase offset of the second signal at the at least one position satisfies a quality criterion related to the phase offset of the first signal.

A digital amplifier includes a digital PWM generator, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, an attenuator, an error extractor, an adder, and a voltage supply unit. The first amplifier circuit amplifies a digital PWM signal at a second voltage. The first low-pass filter extracts a low-frequency band voltage signal from the amplified digital PWM signal, and outputs the extracted voltage signal to a load. The second amplifier circuit amplifies the generated digital PWM signal at a third voltage. The error extractor extracts an error signal. The adder adds a digital error signal whose feedback gain is adjusted to a digital audio signal. The voltage supply unit generates the third voltage that has a voltage value of a predetermined ratio to a voltage value of the second voltage, and supplies the third voltage to the second amplifier circuit.

A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

Methods and systems are provided for spreading spectral density of digital-to-analog conversion output signals. A spreading circuit may spread a digital-to-analog converter (DAC) output signal over a particular frequency spectrum, with the spreading circuit receiving the DAC output signal; generating a plurality of internal control signals; and generating based on the DAC output signal and the one or more internal control signal a corresponding spread output signal. The Internal control signals may comprise at least a first control signal, generated based on sequences meeting at least one particular criterion, a second control signal, generated based on a feedback corresponding to an intermediate output generated within the spreading circuit. The spreading circuit may generate the first control signal based on zero-sum sequences. The spreading circuit may generate a stream of pulses based on the intermediate output, and may generate the feedback signal based on the stream of pulses.

An audio system can include an amplifier having two parallel drivers, one having common source transistors and one having common drain transistors, also called source following. At low signals, the source followers dominate the open-loop gain signal path, while large signals cause the common source transistors to be dominant. At low signal amplitudes, the common source transistor gain is reduced and the common drain transistors provide the load current. At a pre-determined level of signal amplitude, the common source transistors take over and provide the current load. A calibration system for a DAC is also provided. The calibration system measures individual cell performance in the DAC, then stores its digital equivalent in a coefficient storage. Then, a quantizer can refer to the stored coefficients when selecting the appropriate final quantized digital value.

Systems, devices, and methods for a high-voltage conversion circuit system comprising: an error detection and correction module configured to receive an analog input signal and a feedback signal and generate a correction signal; and an analog to pulse width modulation (PWM) module configured to receive the analog input signal and correction signal and generate a PWM output signal; where the generated PWM output signal is fed back to the error detection and correction module as said feedback signal.

Methods and systems are provided for spreading spectral density of digital-to-analog conversion output signals. A spreading circuit may spread a digital-to-analog converter (DAC) output signal over a particular frequency spectrum, with the spreading circuit receiving the DAC output signal; generating a plurality of internal control signals; and generating based on the DAC output signal and the one or more internal control signal a corresponding spread output signal. The Internal control signals may comprise at least a first control signal, generated based on sequences meeting at least one particular criterion, a second control signal, generated based on a feedback corresponding to an intermediate output generated within the spreading circuit. The spreading circuit may generate the first control signal based on zero-sum sequences. The spreading circuit may generate a stream of pulses based on the intermediate output, and may generate the feedback signal based on the stream of pulses.

Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.

Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be reset so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.

Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.