An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 W).

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 W).

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 W).

A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

In accordance with an embodiment, a method of monitoring a data converter includes determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.

In accordance with an embodiment, a method of monitoring a data converter includes determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.

A time-interleaved digital-to-analog converter system, comprising a digital pre-distorter configured to receive an input digital signal and an error signal and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal to an analog signal; and a calibration system. The calibration system includes an analog-to-digital converter having a second sample rate equal to or lower than the first sample rate, the analog-to-digital converter configured to receive the analog signal and covert the analog signal to a down-sampled digital signal, a discrete-time linear model configured to receive the input digital signal and the error signal and output a model signal, and a combiner to subtract the down-sampled digital signal from the model signal to generate the error signal.

A time-interleaved digital-to-analog converter system, comprising a digital pre-distorter configured to receive an input digital signal and an error signal and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal to an analog signal; and a calibration system. The calibration system includes an analog-to-digital converter having a second sample rate equal to or lower than the first sample rate, the analog-to-digital converter configured to receive the analog signal and covert the analog signal to a down-sampled digital signal, a discrete-time linear model configured to receive the input digital signal and the error signal and output a model signal, and a combiner to subtract the down-sampled digital signal from the model signal to generate the error signal.