The present disclosure provides an analog-digital hybrid integrator circuit which includes an operational amplifier coupled to an input terminal, a first capacitor coupled to the input terminal in parallel with the operational amplifier, a plurality of second capacitors coupled in parallel with the first capacitor, and a plurality of buffers that is coupled in series and is coupled in parallel with the plurality of second capacitors, respectively.

A sigma-delta converter comprises a sigma-delta modulator suitable for supplying a series of binary samples (BS(k)) representative of an analogue input signal (Vin) to be digitized, in which at least one analogue signal internal to the modulator is weighted by a coefficient that is variable according to a first predetermined law (f).

Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer with a negative capacitor circuit and a feedback circuit. The receiving circuit is arranged for receiving an input signal and a feedback signal to generate a first signal. The loop filter is coupled to the receiving circuit, and is arranged for receiving the first signal to generate a filtered signal. The quantizer is coupled to the loop filter, and is arranged for generating a digital output signal according to the filtered signal, wherein the negative capacitor circuit is arranged at an input terminal of the quantizer. The feedback circuit is arranged for receiving the digital output signal to generate the feedback signal.

A sigma-delta converter comprises a sigma-delta modulator suitable for supplying a series of binary samples (BS(k)) representative of an analogue input signal (Vin) to be digitized, in which at least one analogue signal internal to the modulator is weighted by a coefficient that is variable according to a first predetermined law (f).

A distortion compensator 10 acquires an asymmetric component included in a 1-bit pulse train outputted from a DSM 6 on the basis of an analog signal as an output signal obtained from the 1-bit pulse train, and an IQ signal as an input signal to be inputted to the DSM 6, and performs distortion compensation on the basis of the asymmetric component. The distortion compensator 10 is caused to store therein asymmetric component data representing the acquired asymmetric component. When acquiring the asymmetric component, the distortion compensator 10 acquires, as an asymmetric component, a difference between an output baseband signal obtained by orthogonally demodulating the analog signal as the output signal, and an input baseband signal before being orthogonally modulated.

A sigma-delta converter including a sigma-delta modulator including at least one analog filter capable, for each cycle of a conversion phase, of receiving an internal analog signal originating from the analog input signal and of supplying an analog output signal, wherein: the contribution of the internal analog signal to the output value of the filter is smaller at a given cycle of the conversion phase than at a previous cycle, the contributions to the different cycles being governed by a first predetermined law which is a function of the rank of the cycle; and the duration of a given cycle of the conversion phase is shorter than the duration of a previous cycle, the durations of the different cycles being governed by a second predetermined law which is a function of the rank of the cycle in the conversion phase.

An analog/digital converter (ADC) includes an analog stage with at least one first sigma-delta modulator and includes a digital stage with at least one second sigma-delta modulator. The analog stage is configured for outputting a digital signal to the digital stage that is indicative of a noise contribution of the at least one first sigma-delta modulator. The analog stage and the digital stage may be arranged in a multi-stage noise shaping architecture (MASH) architecture.

Typically, complex systems require a separate and expensive equalizer at the output of an analog-to-digital converter (ADC). Rather than providing a separate equalizer, the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation. The modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well. As a result, the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet.