A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

For a radio frequency (RF) receiver system (1) for providing magnetic resonance (MR) information from an examination space of a MR imaging system, a solution for increasing the dynamic range of the radio frequency (RF) receiver system (1) for a better imaging performance shall be created. A sigma delta ADC of the RF receiver system operates in single-bit mode with an automatic gain control (AGC) circuit used to control the DAC feedback strength thereby extending the dynamic range of the receiver to match the MRI signal. The present invention also refers to a magnetic resonance (MR) imaging system, a method A method for extending the dynamic range of a radio frequency (RF) receiver system, a software package for a magnetic resonance (MR) imaging system, a software package for upgrading a magnetic resonance (MR) imaging system and a computer program product.