A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.

A detector comprising: a filter arrangement configured to receive an output from a sigma-delta analogue to digital, SD-ADC, converter and generate a filtered output; a threshold comparison element configured to receive the filtered output and determine if signal content present in the filtered output is above or below a predetermined threshold, and wherein the detector is configured to, based on the determination of the threshold comparison element, output a flag signal indicative of a determination that the output of the SD-ADC is one of stable or unstable.

The systems and methods discussed herein related to analog to digital conversion. An apparatus can include an analog to digital converter including a loop circuit and a comparator circuit. The apparatus can also include a first circuit configured to provide comparator offset calibration for the comparator circuit and a second circuit configured to provide loop calibration for the loop circuit.