Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816). The at least one sigma-delta modulator (316, 416, 616, 816) comprises an input (315, 415, 602, 801, 802, 902) configured to receive multiple multi-phase input signals and the controller (340, 440, 640, 840) is configured to adjust the at least one signal-feedforward coefficient (603, 604, 605) of the at least one sigma-delta modulator (316, 416, 616, 816) when combining the multiple multi-phase input signals.

The present disclosure a switched-mode power supply using a reconfigurable delta-signal modulator (DSM). The switched-mode power supply comprises, a current sensing unit configured to determine an operation mode on the basis of a result of sensing a current of an output terminal; a compensator configured to output a compensation signal by amplifying a difference value between an output voltage and a reference voltage; a reconfigurable DSM configured to output a digital signal by noise-shaping the compensation signal; a power switch unit switched by the digital signal to output an output voltage; and an attenuator configured to supply a feedback voltage of the output voltage attenuated by a voltage divider to the compensator.

Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

Each of a plurality of analog-to-digital (AD) converters configuring a column AD converter used in an image sensor comprises: an oversampling AD converter that receives an output voltage of a pixel unit; a recursive AD converter that receives an analog residual signal of the oversampling AD converter; and a counter that adds a digital signal output from the oversampling AD converter and a digital signal output from the recursive AD converter. The controller dynamically allocates the number of bits of the oversampling AD converter and the number of bits of the recursive AD converter, while maintaining the total number of bits of the oversampling AD converter and the recursive AD converter.

Each of a plurality of analog-to-digital (AD) converters configuring a column AD converter used in an image sensor comprises: an oversampling AD converter that receives an output voltage of a pixel unit; a recursive AD converter that receives an analog residual signal of the oversampling AD converter; and a counter that adds a digital signal output from the oversampling AD converter and a digital signal output from the recursive AD converter. The controller dynamically allocates the number of bits of the oversampling AD converter and the number of bits of the recursive AD converter, while maintaining the total number of bits of the oversampling AD converter and the recursive AD converter.

In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.

A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.