An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

Disclosed are an analog-to-digital converter (ADC), an electronic device including the ADC, and an operating method of the ADC. The ADC includes a first stage that includes a plurality of channels, generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving, and generates a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal, an amplifier that amplifies the first residual signal, and a second stage that includes a plurality of channels, generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and generates a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal. The number of the plurality of channels included in the first stage is odd-numbered.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.

Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.