A signal processing circuit has a first signal loop with a first signal processing block and a first feedback path that extends around the first signal processing block, the first signal processing block having a frequency dependence that causes the first signal loop to generate a passband. A second signal processing block is downstream of the first signal loop. A second feedback path extends from downstream of the second signal processing block to upstream of the first signal processing block. In operation, the first feedback path reinforces a signal in the passband and the second feedback path conditions the signal at an output downstream of the first signal processing block.

Asynchronous electrical circuitry produces a stationary carrier signal and encodes a system input signal amplitude into output signal time-sequence information by establishing at a digitizer an operating point value as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal representing the system input signal. An asynchronous time delay is introduced to produce the pulse-width modulated system output signal. The circuitry performs digital-to-analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal. The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

Reduction in signal intensity of a harmonic component included in an output of a delta-sigma modulator is suppressed. A signal processing device includes: a delta-sigma modulator 11 that outputs a pulse signal; a first processor 12 that generates, from the pulse signal P.sub.O outputted from the delta-sigma modulator 11, a discontinuous pulse signal P.sub.C in which each of one-pulse sections in the pulse signal P.sub.O has a low level region on at least one of a rear end and a front end of the one-pulse section; and a second processor that generates a short-width pulse signal P.sub.S having a pulse width shorter than a pulse width of the discontinuous pulse signal P.sub.C generated by the first processor 12.

An exemplary apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal includes: an input line for accepting an input signal; a delay element with an input coupled to the input line and an output; a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output; an integrator having an input coupled to the output of the detector and an output; and an output line coupled to the output of the integrator. The delay element introduces a time delay which is greater than zero and less than twice the nominal oscillation period of the input signal. The detector performs a differencing operation. The integrator has a time constant of integration that is smaller than twice the delay applied by the delay element.

Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.

An analog to digital conversion circuit of a touch screen computing device includes a plurality of analog to digital converter circuits operable to convert a plurality of analog signals into a plurality of digital signals at an oversampling rate, a digital decimation filtering module operable to convert the plurality of digital signals into a plurality of digital filtered signals at a first output rate, a coefficient processor operable to generate real component coefficients and imaginary component coefficients of a filtering function at a plurality of frequencies, a first bandpass filter circuit operable to produce first affect values at known frequencies of the plurality of frequencies, and a second bandpass filter circuit operable to produce second affect values at selected frequencies of the plurality of frequencies.

Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a bandpass noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The bandpass noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

Asynchronous electrical circuitry (400, 500, 600, 700, 800, 900) produces a stationary carrier signal (470, 470) and encodes a system input signal (460, 460) amplitude into output signal time-sequence information by establishing at a digitizer (410, 510, 610, 710, 810, 910) an operating point value (416, 516, 616, 716, 816, 916) as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal (470, 470) corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal (480, 480) representing the system input signal. An asynchronous time delay (t(s)) is introduced to produce the pulse-width modulated system output signal (y(s)). The circuitry performs digital to analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal (490, 490). The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.

A distortion compensator 10 acquires an asymmetric component included in a 1-bit pulse train outputted from a DSM 6 on the basis of an analog signal as an output signal obtained from the 1-bit pulse train, and an IQ signal as an input signal to be inputted to the DSM 6, and performs distortion compensation on the basis of the asymmetric component. The distortion compensator 10 is caused to store therein asymmetric component data representing the acquired asymmetric component. When acquiring the asymmetric component, the distortion compensator 10 acquires, as an asymmetric component, a difference between an output baseband signal obtained by orthogonally demodulating the analog signal as the output signal, and an input baseband signal before being orthogonally modulated.