An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

An analog-to-digital converter (ADC) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Methods and systems for inspecting a product, such as a wire harness, including product features for inspection. A camera of an inspection station may capture a product image. A machine learning (ML) model may detect one or more objects in the captured product image and provide, for each detected object, an identification of a class of the detected object and an identification of a region of the detected object in the captured product image. The class of the detected object may be either an acceptable product feature class or an unacceptable product feature class. The inspection station may display an enhanced product image that includes the captured product image to which the identification of the class of the detected object and the identification of the region of the detected object in the captured product image for each detected object have been added.

A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.

A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.