An analog-to-digital converter comprises a first quantizer arranged for yielding a first digital signal; an error signal generation block arranged for generating an error signal representative of a difference between an analog input signal and the first digital signal; an analog loop filter arranged for receiving the error signal; a second quantizer arranged for receiving an output signal of the analog loop filter and for outputting a second digital signal; a digital loop filter arranged for receiving the second digital signal and for providing an input signal to the first quantizer; and a recombiner block comprising a first recombination and a second recombination filter, and an adder circuit for adding outputs of the first and second recombination filters. The first and second recombination filters are selected to obtain an analog-to-digital converted output signal being less dependent on quantization noise caused by the first quantizer than a first digital signal.

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

An analog-to-digital converter comprises a first quantizer arranged for yielding a first digital signal; an error signal generation block arranged for generating an error signal representative of a difference between an analog input signal and the first digital signal; an analog loop filter arranged for receiving the error signal; a second quantizer arranged for receiving an output signal of the analog loop filter and for outputting a second digital signal; a digital loop filter arranged for receiving the second digital signal and for providing an input signal to the first quantizer; and a recombiner block comprising a first recombination and a second recombination filter, and an adder circuit for adding outputs of the first and second recombination filters. The first and second recombination filters are selected to obtain an analog-to-digital converted output signal being less dependent on quantization noise caused by the first quantizer than a first digital signal.

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

Methods and systems for inspecting a product, such as a wire harness, including product features for inspection. A camera of an inspection station may capture a product image. A machine learning (ML) model may detect one or more objects in the captured product image and provide, for each detected object, an identification of a class of the detected object and an identification of a region of the detected object in the captured product image. The class of the detected object may be either an acceptable product feature class or an unacceptable product feature class. The inspection station may display an enhanced product image that includes the captured product image to which the identification of the class of the detected object and the identification of the region of the detected object in the captured product image for each detected object have been added.

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.

A digital transmitter includes baseband interfaces to generate digital baseband signals with baseband frequencies, digital-upconverting stages to upconvert the baseband frequencies to first radio frequencies having a predetermined frequency range, a M-Band M modulator to modulate the up-stage signals based on noise shaping and noise quantization processes, delay registers to align phases of the modulated up-stage signals, a noise canceler to generate noise canceling signals with a converted polarity, a Switch Mode Power Amplifier to amplify the phase aligned modulated up-stage signals up to a predetermined power level, a linear power amplifier to amplify the noise canceling signals up to the predetermined power level, a power combiner to combine to generate transmitting signals by combining the amplified phase aligned modulated up-stage signals and the amplified noise canceling signals, and an antenna to transmit the transmitting signals.

A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.