A second-order ΔΣ modulator includes: a two-stage integrator; a first arithmetic operation circuit; and a second arithmetic operation circuit. The two-stage integrator includes a plurality of adder arrays, each of which includes a plurality of adders. The plurality of adder arrays includes first to fourth adder arrays. An output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array. An output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array. A sum bit string obtained in the first adder array is input to the third adder array. A sum bit string obtained in the second adder array is input to the fourth adder array.

The application describes method and apparatus for amplification. An amplifier circuit (300) is described for driving a load (101) connected between first and second output nodes (103p, 103n) based on an input signal (Sin). The amplifier circuit includes first and second signal paths for generating respective first and second driving signals (Soutp and Soutn) at the first and second output nodes, each of the first and second signal paths comprising a respective sigma-delta modulator (301p, 301n). A correlation controller (302) is configured to control the first and second signal paths to provide correlation between at least some noise components of the first and second driving signals.

A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.

One example method of operation may include one or more of identifying a calling device number of a calling device, matching the calling device number with one or more of a plurality of enhanced call content profiles, selecting, based on a call identifier, one of the enhanced call content profiles comprising enhanced call content intended for one or more call recipient device numbers, and forwarding the enhanced call content associated with the selected enhanced call content profile to one of the call recipient devices.

One example method of operation may include one or more of identifying a calling device number of a calling device, matching the calling device number with one or more of a plurality of enhanced call content profiles, selecting, based on a call identifier, one of the enhanced call content profiles comprising enhanced call content intended for one or more call recipient device numbers, and forwarding the enhanced call content associated with the selected enhanced call content profile to one of the call recipient devices.

A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output.

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant.

A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.