An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.

In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.

The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.

A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.