An image sensor may include an array of image pixels arranged in rows and columns. A first portion of the array may include active pixels that are read out using first analog-to-digital converter (ADC) circuits. A second portion of the array may include dark reference pixels that are read out using second analog-to-digital converter (ADC) circuits. The first ADC circuits may have a first sampling rate, a first resolution, and a first size. The second ADC circuits may have an oversampling rate that is greater than the first sampling rate, a second resolution that is greater than the first resolution, and a second size that is bigger than the first size. Configured in this way, the second ADC circuits may perform averaging of a row noise via direct time-domain oversampling, which can help dramatically reduce the number of dark reference pixel columns in the array.

A compressive sensing image sensor includes: a pixel array; and a readout circuit configured to receive pixel data on a shot image in an analogue form, and to process the pixel data, wherein the pixel array includes a plurality of blocks each having a plurality of pixels and arranged in an array form, wherein the circuit includes: a compressive sensing multiplexer to which a plurality of pixel data outputted from a corresponding block from among the plurality of blocks are inputted; an LFSR configured to arbitrarily select at least one pixel data from the plurality of pixel data inputted to the compressive sensing multiplexer; and a delta-sigma ADC configured to receive the at least one pixel data selected by the LFSR, to delta-sigma modulate the received at least one pixel data, and to generate compressive sensing data for restoring an image of the corresponding block from among the shot images.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

A multiplexed sigma-delta analog-to-digital converter (ADC) is provided for digitizing analog input signals of at least two input channels. The ADC includes input circuitry that obtains samples of the input channels and an integrator chain. The integrator chain includes a first delaying integrator and a second delaying integrator. The first delaying integrator processes a sample of one of the two input channels at a time. A first non-delaying integrator is disposed in the integrator chain either between the first delaying integrator and the second delaying integrator or after the second delaying integrator. A clocking arrangement includes a first clock set and a second clock set. Channel selection clocks included in the second clock set are delayed in comparison to the respective channel selection clocks included in the first clock set in order to prevent data from being mixed between consecutive full clock cycles.

An isolator of embodiments includes a ΔΣ analog-digital converter configured to convert an analog signal into a digital signal of one bit and transmit the digital signal of one bit as normal data, a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from the normal data, and an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.

A digital lock-in controller for Resonant-type converters with one or more sub-circuits having resonant tanks and one or more flying capacitors connected across the resonant tanks, which comprises an auto-tuner that receives as input Zero-Current Detect (ZCD) signals and implements a tuning algorithm by performing arithmetic operations that ensure Zero-Current Switching (ZCS) operation for all resonant tanks in the converter; a digital hybrid High-Resolution (HR) sequencer that receives as input the switching times commands and generates a pulse-width-modulated signal that is fed into the gates of the converter's switching transistors; a sampling block with time resolution of a single delay-element, for accurately reading of the ZCD sensor's outputs; a governor module for performing all synchronization actions and dictating the operation mode of the controller, based on auxiliary configurations.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit 126 due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.

Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.

An analog-to-digital converter (ADC) includes an input circuit configured to receive a first analog signal output from a first sensor or a second analog signal output from a second sensor according to an operation mode and a bit stream; a filter configured to filter an output signal from the input circuit; a quantization circuit configured to generate the bit stream from an output signal of the filter; and a digital circuit configured to generate a first digital signal corresponding to the first analog signal or a second digital signal corresponding to the second analog signal by filtering the bit stream, wherein the operation mode includes a first mode selecting the first sensor and a second mode selecting the second sensor, and wherein the digital circuit refers to the second digital signal generated during the second mode to generate the first digital signal during the first mode.