A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.

Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.

A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

A digital sigma-delta modulator may be provided that includes: a multiplexer which receives N-bit input data from each of M number of input terminals and sequentially outputs; an adder which outputs carry out (CO) data and N-bit added data obtained by adding the N-bit input data and N-bit added data output in a previous cycle; a memory which divides the N-bit added data output from the adder into A-bit added data and (NA)-bit added data and stores the A-bit added data and the (NA)-bit added data; and a demultiplexer which receives the output carry out (CO) data and outputs to each of M number of output terminals.

In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

A radio frequency (RF) transmitter includes a set of input ports to receive baseband, a set of filter banks for each input port that includes a plurality of digital polyphase interpolation filters, and a set of oscillators banks, wherein each oscillator bank includes a plurality of polyphase Digital Direct Synthesizer (DDS) corresponding to the plurality of digital polyphase interpolation filters. The RF transmitter includes a set of mixer banks to mix corresponding sequences of samples of digital waveform, a parallel digital combiner to combine in-phase sequences of interpolated baseband phased samples, and a pulse encoder to modulate and encode the plurality of sequences of multiband upconverted samples. The RF transmitter converts a plurality of encoded multi-band signals into a RF bitstream and an E/O interface to convert the RF bitstream.

A high-speed digital transmitter for wireless communication systems includes a plurality of transmitter chain circuits configured to respectively receive incoming component signals having a first frequency and to produce outgoing transmission signals having a second frequency greater than the first frequency in a first domain. In some aspects, the incoming component signals are up-sampled to the second frequency using a plurality of streams processed concurrently at a predetermined sample rate over a predetermined number of interpolation filter stages in each of the plurality of transmitter chain circuits. The high-speed digital transmitter also includes a serializer configured to combine the outgoing transmission signals from the plurality of transmitter chain circuits into a serialized transmission signal having a third frequency greater than the second frequency in a second domain different from the first domain.

An apparatus comprises: a plurality of analog-to-digital conversion units that performs analog-to-digital conversion using ?? modulation by comparing a signal output from a plurality of pixels to a reference voltage; and a plurality of supply units that supply one of a plurality of different reference voltages to each of the plurality of analog-to-digital conversion units. The plurality of supply units supply different reference voltages to adjacent analog-to-digital conversion units among the plurality of analog-to-digital conversion units.

An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.