A readout circuit includes a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array. A second analog circuit is configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array. A first digital circuit is configured to receive the first signal and convert the first signal to a first digital signal, and receive the second signal and convert the second signal to a second digital signal.

A system may include a delta-sigma analog-to-digital converter and a digital compression circuit. The delta-sigma analog-to-digital converter may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, a multi-bit quantizer configured to quantize the intermediate signal into an uncompressed digital output signal, and a feedback digital-to-analog converter having a feedback output configured to generate a feedback output signal responsive to the uncompressed digital output signal in order to combine the input signal and the feedback output signal at the loop filter input. The digital compression circuit may be configured to receive the uncompressed digital output signal and compress the uncompressed digital output signal into a compressed digital output signal having fewer quantization levels than that of the uncompressed digital output signal.

A cellular radio architecture for a vehicle that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a triplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the triplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the triplexer.

An encoding apparatus comprises a frame processor (105) which receives a multi channel audio signal comprising at least a first audio signal from a first microphone (101) and a second audio signal from a second microphone (103). An ITD processor 107 then determines an inter time difference between the first audio signal and the second audio signal and a set of delays (109, 111) generates a compensated multi channel audio signal from the multi channel audio signal by delaying at least one of the first and second audio signals in response to the inter time difference signal. A combiner (113) then generates a mono signal by combining channels of the compensated multi channel audio signal and a mono signal encoder (115) encodes the mono signal. The inter time difference may specifically be determined by an algorithm based on determining cross correlations between the first and second audio signals.

A system may include a delta-sigma analog-to-digital converter and a digital compression circuit. The delta-sigma analog-to-digital converter may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, a multi-bit quantizer configured to quantize the intermediate signal into an uncompressed digital output signal, and a feedback digital-to-analog converter having a feedback output configured to generate a feedback output signal responsive to the uncompressed digital output signal in order to combine the input signal and the feedback output signal at the loop filter input. The digital compression circuit may be configured to receive the uncompressed digital output signal and compress the uncompressed digital output signal into a compressed digital output signal having fewer quantization levels than that of the uncompressed digital output signal.

A multiplexed sigma-delta analog-to-digital converter (ADC) is provided for digitizing analog input signals of at least two input channels. The ADC includes input circuitry that obtains samples of the input channels and an integrator chain. The integrator chain includes a first delaying integrator and a second delaying integrator. The first delaying integrator processes a sample of one of the two input channels at a time. A first non-delaying integrator is disposed in the integrator chain either between the first delaying integrator and the second delaying integrator or after the second delaying integrator. A clocking arrangement includes a first clock set and a second clock set. Channel selection clocks included in the second clock set are delayed in comparison to the respective channel selection clocks included in the first clock set in order to prevent data from being mixed between consecutive full clock cycles.

Disclosed herein is an apparatus for measuring a voltage. The apparatus includes a primary integrator circuit configured to operate as a first integral stage of a sigma-delta analog-to-digital converter circuit when switched by a first control signal from a controller, a secondary integrator circuit configured to operate as a second integral stage when switched by a second control signal from the controller, a comparator configured to compare final voltages modulated through the primary integrator circuit and the secondary integrator circuit, and a digital filter configured to delay an output of the comparator by a specified number of clocks according to a switching of the controller, pass the delayed output through a digital-to-analog converter (DAC) to feed the delayed output back to the primary and secondary integrator circuits, and receive the delayed output signal of the comparator as an input. An output of the digital filter becomes a final measured value.

An encoding apparatus comprises a frame processor (105) which receives a multi channel audio signal comprising at least a first audio signal from a first microphone (101) and a second audio signal from a second microphone (103). An ITD processor 107 then determines an inter time difference between the first audio signal and the second audio signal and a set of delays (109, 111) generates a compensated multi channel audio signal from the multi channel audio signal by delaying at least one of the first and second audio signals in response to the inter time difference signal. A combiner (113) then generates a mono signal by combining channels of the compensated multi channel audio signal and a mono signal encoder (115) encodes the mono signal. The inter time difference may specifically be determined by an algorithm based on determining cross correlations between the first and second audio signals.

An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal.

The present disclosure provides a clock circuit and related method improving frequency hopping. The clock circuit may comprise a frequency divider and a frequency hopping circuit. The frequency divider may perform a frequency division according to a first divisor number. When hopping to a frequency or a spread spectrum range which is corresponding to an input number, if a convergence condition is not satisfied, the frequency hopping circuit may perform a stepping operation to update the first divisor number from a previous value to a current value which may not equal the input number.