The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample. The objective is also solved by a method using the aforementioned analog-to-digital converter.

A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.

A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.

A multiplexed sigma-delta analog-to-digital converter (ADC) is provided for digitizing analog input signals of at least two input channels. The ADC includes input circuitry that obtains samples of the input channels and an integrator chain. The integrator chain includes a first delaying integrator and a second delaying integrator. The first delaying integrator processes a sample of one of the two input channels at a time. A first non-delaying integrator is disposed in the integrator chain either between the first delaying integrator and the second delaying integrator or after the second delaying integrator. A clocking arrangement includes a first clock set and a second clock set. Channel selection clocks included in the second clock set are delayed in comparison to the respective channel selection clocks included in the first clock set in order to prevent data from being mixed between consecutive full clock cycles.

An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.

A gain stage, such as an amplifier, e.g., an instrumentation amplifier, can receive an input signal and adjust the level of the input signal, e.g., amplify or attenuate. An output voltage of the gain stage can be applied to a subsequent circuit. Using various techniques, a second stage of an instrumentation amplifier, which can include a transconductance stage that converts a current to a voltage that can be applied to an output node of the instrumentation amplifier, can be removed. Removal of such a second stage can allow an output current from the gain stage to be applied directly from a current output node to an input node of a subsequent circuit.

A photoelectric conversion apparatus includes a light receiving circuit configured to convert light into an electrical signal, a readout circuit configured to read out an analog signal corresponding to the electrical signal, a ΔΣ A/D converter configured to convert the analog signal into a digital signal, and a control circuit configured to change a gain of the photoelectric conversion apparatus in accordance with a change of a driving mode of the photoelectric conversion apparatus. The analog signal read out by the readout circuit is an analog current signal. The readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A/D converter. The control circuit changes the gain of the photoelectric conversion apparatus by changing a resistance value of the variable resistor.