Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, n.sup.th order resonant bandpass filtering with n>1, and signal sub-sampling in an i.sup.th Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using n.sup.th order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95dB.

A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.

Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, n.sup.th order resonant bandpass filtering with n>1, and signal sub-sampling in an i.sup.th Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using n.sup.th order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

An RF signal generation device includes an RF signal generation unit 102 that pulse-modulates a prescribed signal to generate an output signal in which four or more-level discrete output levels appear and that a lowest level and any other level appear alternately; a code converter 91 that converts the output signal from the RF signal generation unit 102 into an RF signal in which a smaller number of levels than the number of levels in the output signal; a driver unit 203 that converts the RF signal from the code converter 91 into a binary signal comprising plural bits in which bits corresponding to signal levels in the RF signal are significant; and a digital amplifier 303 that outputs a voltage corresponding to levels in the RF signal outputted from the code converter 91, on the basis of an output signal from the driver unit 203.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

A signal converter includes a first converter, a second converter, a signal generator, and a controller. The first converter generates a first analog signal from a digital signal, and the second converter generates a second analog signal from the digital signal. The signal generator outputs a converted analog signal based on the first analog signal and the second analog signal. The controller generates one or more control signals to change a power supply state of at least one of the first converter and the second converter. The change in power supply state suppress even order harmonics.

A digital to analog converter that includes a delta sigma modulator coupled to receive a digital data. The delta sigma modulator supplies a multi-bit resistor digital to analog converter (DAC). The multi-bit resistor digital to analog converter supplies an amplifier with an analog signal corresponding to the digital data. A first low pass filter is coupled between the multi-bit digital to analog converter and the amplifier stage and filters out shaped quantization noise before it reaches the amplifier. A second low pass filter is coupled to an output of the amplifier stage and filters out residual quantization noise and chopping artifacts from the amplifier stage.