H03M5/14

Vector signaling code with improved noise margin
11240076 · 2022-02-01 · ·

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Data storage on implantable magnetizable fabric
11234806 · 2022-02-01 · ·

The disclosure is directed to a system, device and method for data storage on implantable magnetizable fabric. The system includes implantable magnetizable fabric coupled to a graft segment of a prosthesis for being delivered into a body of a subject. The system includes information written on the implantable magnetizable fabric. The system further includes a magnetic detection device capable of, after the prosthesis is delivered into the body of the subject, detecting the implantable magnetizable fabric and accessing at least a portion of the information.

Passive multi-input comparator for orthogonal codes on a multi-wire bus

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

Inversion signal generation circuit
11152042 · 2021-10-19 · ·

An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.

DC-balanced, transition-controlled, scalable encoding method and apparatus for multi-level signaling

The present invention relates to an encoding apparatus for multi-level signaling, the encoding apparatus including: a candidate pattern generator (1) generating a set of candidate patterns from input data by using symbol-based inversion; a controller (2) generating a cumulated disparity value that is a result of calculating disparity indicating a degree to which transmission data up to previous transmission deviates from DC balance, storing the cumulated disparity value, and determining a transmission control code by using the cumulated disparity value and a set of disparity values that is a result of calculating disparity indicating a degree to which each of the candidate patterns deviates from DC balance; and a data selector (3) selecting one candidate pattern from the set of the candidate patterns as data to be transmitted, according to the determined transmission control code.

DIRECT MAPPING

A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

DIRECT MAPPING

A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

HIGH SPEED INTERCONNECT SYMBOL STREAM FORWARD ERROR-CORRECTION
20210314086 · 2021-10-07 · ·

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Converting a single-bit audio stream to a stream of symbols with a constant edge rate

A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

Converting a single-bit audio stream to a stream of symbols with a constant edge rate

A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.