Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

In certain aspects, a circuit for modulo-3 operation has an encoder stage coupled to a binary number, wherein the encoder stage includes one or more encoders, each one of the one or more encoders receives one or two binary bits of the binary number and generates a unary code of encoder. The circuit for modulo-3 operation further has one or more levels of reduction stage, wherein a first level of the one or more levels of reduction stage includes one or more mergers of first reduction, each one of the one or more mergers of first reduction receives two unary codes of encoder or a unary code of encoder and a bit from the binary number and generates a unary code of first reduction.

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0-90, 90-180, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

Systems and methods relate to interpolating values in a transfer function between a first parameter (e.g., temperature) and a second parameter (e.g., voltage). A decoder is configured to receive a temperature value and multiple trim codes each corresponding to one temperature. Decoder and adder circuitry is configured to receive the temperature value from the decoder and to receive two closest trim codes of the plurality of trim codes corresponding to two closest temperatures of the temperatures that are closest to the temperature value. The decoder and adder circuitry then calculates an output trim code based at least in part on the two closest trim codes; outputs the trim code.

A family of current mode analog to digital converters, or TiADC, utilizing methods, circuits, and apparatuses, are disclosed with the following benefits: (1) There are normal and random non-systematic mismatch between devices in silicon manufacturing, that introduce non-linearity in current mode analog to digital converter's, or iADC, reference network. The iADC's linearity is improved by utilizing a thermometer current mode signal conditioning method, SCM. Successive applications of the SCM effectuates a segmented current reference network to function like a thermometer network, which operates based on the function of summation. Having a TiADC with a thermometer reference network, where current segments are summed or accumulated incrementally, would inherently reduce the impact of statistical distribution of component's random mismatch on the iADC's non-linearity. Accordingly, linearity of TiADC can be improved by the square root of the sum of the square of mismatch errors of the number of segmented current references in the thermometer network. (2) speed is improved by operating the TiADC in current mode, which is inherently faster. (3) voltage swings in current mode are small, which enables he iADC to operate at lower power supply voltages. (4) The TiADC can operate in subthreshold and at very low currents, which lower powers consumption. (5) the TiADC is asynchronous. Being clock free, TiADC has lower dynamic power consumption with reduces digital system noise. (6) the signal conditioning method or SCM utilized in TiADC provides concurrent functions of analog differencing and digital comparison. This trait enhances the dynamic response of iADC, wherein the digital output throughput accuracy degrades gradually and not abruptly as a function of increasing frequency of iADC's input signal. (7) No passive devices, such as capacitors or resistors, are required for the TiADC. (8) TiADC can be fabricated on low cost mainstream standard digital CMOS processes.

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.