A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

Various examples are directed to a digital predistortion (DPD) circuit comprising a DPD actuator circuit, a DPD feedback frequency-shaping filter, a basis matrix generator circuit, a basis matrix frequency-shaping filter, and a DPD adaption circuit. The DPD actuator circuit may generate a predistorted signal based at least in part on an input signal and a set of frequency-shaped DPD parameters. The DPD feedback frequency-shaping filter may filter a DPD feedback signal to generate a frequency-shaped DPD feedback signal. A passband of the DPD feedback frequency-shaping filter may include substantially all of a bandwidth of the input signal and exclude a distortion term outside the bandwidth of the input signal. The basis matrix generator may generate a basis matrix based at least in part on a power amplifier feedback signal The basis matrix frequency-shaping filter may generate a frequency-shaped basis matrix based at least in part on the basis matrix. The DPD adaption circuit may be configured to generate the set of frequency-shaped DPD parameters based at least in part on the frequency-shaped basis matrix and the frequency-shaped DPD feedback signal.

Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

A digital microphone device includes circuitry that can reduce the risk of noise caused due to an idle tone frequency component in a digital signal output by the digital microphone device. In stereo mode and other applications where interference occurs between two or more such microphones, each microphone device includes a digital output having a corresponding idle tone frequency, one of which is offset to shift noise components outside of a desired frequency range.

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

A decimation filter including a Hadamard-Walsh transform circuit, a comparator, and an inverse Hadamard-Walsh transform circuit. The Hadamard-Walsh transform circuit includes an input receiving a pulse density modulation bitstream and an output providing a stream of digital samples. The comparator replaces each digital sample that has a magnitude below a predetermined threshold value with a zero value and provides adjusted digital samples. The inverse Hadamard-Walsh transform circuit has an input receiving the adjusted digital samples and has an output providing pulse code modulation data values. The decimation filter may further include a down-sampler that down samples the adjusted digital samples by before being provided to the inverse Hadamard-Walsh transform circuit. The decimation filter may include a low pass filter and another down-sampler at the output. The Hadamard-Walsh transform circuits may be implemented according to the fast Hadamard-Walsh transform so that only digital additions and subtractions are performed.

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that permit switching between a plurality of DSD signals having different sampling frequencies using a simple configuration.

An acquisition section acquires a digital audio signal having a given sampling frequency selected from among the plurality of digital audio signals acquired by delta-sigma modulating an audio signal at a plurality of sampling frequencies. An interpolation section subjects the acquired digital audio signal to a pre-interpolation process when the sampling frequency of the acquired digital audio signal is lower than an operating clock of a delta-sigma demodulator. The present technology is applicable, for example, to a signal processing apparatus.

A radio frequency transmitter for wireless communication includes a plurality of input ports to receive a plurality of sequences of baseband symbols to be transmitted on a plurality of disjoint frequency bands, a power encoder to modulate and encode the plurality of sequences of baseband symbols to produce an encoded multi-band signal including the plurality of disjoint frequency bands carrying the plurality of sequences of baseband symbols, a first power amplifier for amplifying the encoded multi-band signal to produce an amplified encoded multi-band signal, a first noise canceller to generate a first noise mitigation signal from the encoded multi-band signal and the plurality of sequences of baseband symbols, a first power combiner to combine the amplified encoded multi-band signal and the first noise mitigation signal to produce an RF multi-band signal, and an antenna for transmitting the RF multi-band signal.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.