H03M7/3086

Data compressor and data compression method

A data compressor with a hash computing hardware configured to evaluate the hash value for the current hash key extracted from a source data string, obtain a hash line corresponding to the hash value from a hash table, and perform hash key comparison to find at least one matching hash key. The hash line includes a prefix address column that stores a prefix address. Each entry of the hash line is provided to store a hash key and an offset. The hash computing hardware evaluates an address of the at least one matching hash key by combining the prefix address and an offset of the at least one matching hash key, and the offset of the at least one matching hash key is obtained from an entry storing the at least one matching hash key.

MEMORY SYSTEM

A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by refferring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.

MEMORY SYSTEM

A memory system including a history buffer, a hash calculator, a read pointer table, a history buffer writing circuit, a read pointer writing circuit, a read pointer reading circuit, a history buffer reading circuit, a matching circuit replacing the input data string with a reference information referring the matching candidate data string in the case where at least a part of the input data string and a part of the matching candidate data string match. Reading of the read pointer by the read pointer reading circuit and reading of the stored input data string by the history buffer reading circuit are executed after writing of the read pointer by the read pointer writing circuit and writing of the input data string by the history buffer writing circuit are finished.

Instant quiescing of an accelerator

A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.

Devices and methods for compression and decompression

A device for compressing first data which are to be compressed comprises a control unit configured to compress the first data based upon further data to obtain compressed data. The control unit is configured to provide memory area information indicative of a memory location of the further data.

Verifying the correctness of a deflate compression accelerator

Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

TECHNOLOGIES FOR ASSIGNING WORKLOADS TO BALANCE MULTIPLE RESOURCE ALLOCATION OBJECTIVES
20210105197 · 2021-04-08 ·

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON SET OF INTERCONNECT CONNECTORS

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

LOW-LATENCY DIRECT CLOUD ACCESS WITH FILE SYSTEM HIERARCHIES AND SEMANTICS

Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

Technologies for dynamically managing resources in disaggregated accelerators

Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.