Technologies for rack cooling includes monitoring a temperature of a sled mounted in a rack and controlling a cooling system of the rack based on the temperature of the sled. The cooling system includes a cooling fan array, which may be controlled to cool the sled. Additionally, if needed, one or more adjacent cooling fan arrays that are located adjacent to the controlled cooling fan array may be adjusted to provide additional cooling to the sled.

A rack for supporting sleds includes a pair of elongated support posts and pairs of elongated support arms that extend from the elongated support posts. Each pair of the elongated support arms defines a sled slot to receive a corresponding sled. A power supply is attached to an elongated support arm of each pair of elongated support arms to provide power to a corresponding sled. The power supply may include a chassis-less circuit board substrate that is removable from a power supply housing coupled to the corresponding elongated support arm.

Examples may include racks for a data center and sleds for the racks, the sleds arranged to house physical resources for the data center. The sleds and racks can be arranged to be autonomously manipulated, such as, by a robot. The sleds and racks can include features to facilitate automated installation, removal, maintenance, and manipulation by a robot.

An encoder for encoding input data to generate corresponding encoded data is provided. The encoder (10) is operable to process a sequence of elements in the input data from a first element thereof to a last element thereof. The elements have corresponding symbols. The encoder is operable to compute probabilities of symbols present in the sequence, wherein the probabilities of the symbols are computed while disregarding those elements of the sequence that have already been encoded into the encoded data. Moreover, the probabilities of the symbols are adaptively changed as the sequence of elements is progressively encoded into the encoded data. Furthermore, information describing the probabilities is delivered; optionally, the probabilities of the symbols are accompanied with additional information indicating how the probabilities are adaptively changing. There is also provided a decoder for performing an inverse of encoding performed by the encoder.

Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.

An encoder includes data processing hardware operable to: process input data into a plurality of blocks/packets; apply a plurality of transformations to content of the blocks/packets to generate corresponding transformed data; check a quality of representation of the transformed data prior to application of the transformations to determine whether or not the quality of representation of the transformed data satisfies quality criteria; if the quality of representation does not satisfy the quality criteria, to divide and/or combine the one or more individual blocks or packets further and repeating the transformation step; and if the quality of representation of the transformed data satisfies the one or more quality criteria, to select coding methods and encode data representative of the input data to be encoded to provide encoded output data; and communicate in the encoded data information describing the plurality of transformations or combinations of transformations employed when coding the blocks/packets.

Examples may include a sled for a rack of a data center including physical storage resources. The sled comprises an array of storage devices and an array of memory. The storage devices and memory are directly coupled to storage resource processing circuits which are themselves, directly coupled to dual-mode optical network interface circuitry. The circuitry can store data on the storage devices and metadata associated with the data on non-volatile memory in the memory array.

A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.

Technologies for managing partially synchronized writes include a managed node. The managed node is to issue a write request to write a data block, on behalf of a workload, to multiple data storage devices connected to a network, pause execution of the workload, receive an initial acknowledgment associated with one of the multiple data storage devices, wherein the initial acknowledgement is indicative of successful storage of the data block, and resume execution of the workload after receipt of the initial acknowledgement and before receipt of subsequent acknowledgements associated with any of the other data storage devices. Other embodiments are also described and claimed.

A processor includes a plurality of packed data registers. The processor also includes a decode unit to decode a packed variable length code point length determination instruction. The instruction is to indicate a first source packed data that is to have a plurality of packed variable length code points that are each to represent a character. The instruction is also to indicate a destination storage location. The processor also has an execution unit coupled with the decode unit and the packed data registers. The execution unit, in response to the instruction, is to store a result packed data in the indicated destination storage location. The result packed data is to have a length for each of the plurality of the packed variable length code points. Other processors, methods, systems, and instructions are also disclosed.