H03M7/4031

Out-of-band management techniques for networking fabrics

Out-of-band management techniques for networking fabrics are described. In an example embodiment, an apparatus may comprise a packet-switched network interface to deconstruct a packet received via an out-of-band management network and control circuitry to execute an out-of-band management agent, and the out-of-band management agent may be operative to identify a configuration command comprised in the received packet and control an optical circuit-switched network interface based on the configuration command. Other embodiments are described and claimed.

Compensation table compression method, display manufacturing apparatus, and memory

The present invention discloses a compensation table compression method, a display manufacturing apparatus, and a memory. The method includes: obtaining a reference frame compensation table and a current frame compensation table; dividing the reference frame compensation table and the current frame compensation table into a plurality of coding blocks, wherein each coding block is separately processed by using multiple prediction modes to obtain a residual coding block in the corresponding prediction mode; and compressing the residual coding block. By using the above method, the invention can save resources, reduce costs, and improve work efficiency.

Speculative data processing and recovery

Aspects include copying a plurality of input data into a buffer of a processor configured to perform speculatively executing pipelined streaming of the input data. A bit counter maintains a difference in a number of input bits from the input data entering a pipeline of the processor and a number of the input bits consumed in the pipeline. The pipeline is flushed based on detecting an error. A portion of the input data is recirculated from the buffer into the pipeline based on a value of the bit counter.

Technologies for dynamically managing resources in disaggregated accelerators

Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

System and method for compression of geospatial location data
11055260 · 2021-07-06 · ·

Systems and methods for the compression and decompression of geospatial locations are disclosed. The compression and decompression are based on a prediction of the geospatial location and a geometrical projection of the Earth.

FAST EVALUATION OF PREDICATES AGAINST COMPRESSED DATA
20210006262 · 2021-01-07 ·

Evaluating LIKE predicates against compressed data. An alphabet, a LIKE predicate, a compressed string, and a compression dictionary for the compressed string are received. Entries in the compression dictionary include a character string and an associated token. The LIKE predicate is converted to an equivalent pattern matching form, involving a search pattern of length m. For each character of the alphabet that appears in a string associated with a token, a mask of predetermined length k is created. For each entry in the compression dictionary a cumulative mask of length k is computed. A bit vector of length k is initialized, based on the search pattern. Successive tokens in the compressed string are processed using a logical shift of the bit vector and a bitwise operation of the bit vector with the cumulative mask associated with the token.

Techniques to support multiple interconnect protocols for a common set of interconnect connectors

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

COMPENSATION TABLE COMPRESSION METHOD, DISPLAY MANUFACTURING APPARATUS, AND MEMORY
20200412377 · 2020-12-31 ·

The present invention discloses a compensation table compression method, a display manufacturing apparatus, and a memory. The method includes: obtaining a reference frame compensation table and a current frame compensation table; dividing the reference frame compensation table and the current frame compensation table into a plurality of coding blocks, wherein each coding block is separately processed by using multiple prediction modes to obtain a residual coding block in the corresponding prediction mode; and compressing the residual coding block. By using the above method, the invention can save resources, reduce costs, and improve work efficiency.

IDENTIFYING FIXED BITS OF A BITSTRING FORMAT
20200394446 · 2020-12-17 ·

Techniques are disclosed for identifying fixed bits of a bitstring format. One or more processors are configured to generate a first bitstring having respective first bit values that have a first satisfiability state and generate a second bitstring having respective second bit values that have a second satisfiability state. The one or more processors are configured to identify first potential free bits having respective first common values and generate a third bitstring having first potential free bits with the respective first common values and third remaining bits. The one or more processors are configured to identify second potential free bits having respective second common values and identify a fixed bit that is not included in the first potential free bits and is not included in the second potential free bits.

METHOD FOR REDUCING READ PORTS AND ACCELERATING DECOMPRESSION IN MEMORY SYSTEMS
20200393970 · 2020-12-17 ·

A decompression system includes a first memory including a first write port configured to receive decompressed data from a decompressor, and a first read port configured to receive a back-reference read request, the first memory being configured to output the decompressed data to the decompressor in response to receiving the back-reference read request at the first read port, and a second memory including a second write port electrically coupled to the first write port and configured to receive the decompressed data, the second memory being configured to buffer the decompressed data for retrieval by a receiver.