A smart sensing architecture (100) includes smart meters (102) and processing units (104). The smart meters (102) generate and transmit multidimensional data streams to the processing units (104). A processing unit (104) determines an optimum batch size for a multidimensional data stream and generates a multidimensional batch of data. The processing unit (104) reduces dimensionality of the multidimensional batch of data using principal component analysis to generate a low-dimensional batch of data and performs compressive sampling on the low-dimensional batch of data to generate a compressed batch of data, thereby saving bandwidth of transmission.

A method for optical communication includes combining jointly source coding with LDPC channel coding into a nonuniform signalling by mapping low-complexity variable-length prefix codes onto a constellation; and performing arbitrary nonuniform signalling, where information bits and parity bits are transmitted with different modulation schemes.

Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an inner ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an outer ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.

An error detection code generating device includes: a detector configured to detect a number of changed bits, which indicates a number of bits changed between transmitted data and a parity of a previous session and transmitted data and a parity of a current session; a generator configured to generate a first add code for a detection of an error based on the number of changed bits detected by the detector and the parity of the transmitted data of the current session; and a compression circuit configured to compress the first add signal generated by the generator and generate a second add code to be added to the transmitted data of the current session.

The present invention is a data transfer system that can transfer, with respect to simulation result data, physical quantities necessary for a user, further perform area division based on characteristics of physical quantities, designate an allowable range of a compression error according to a purpose for each of divided areas, compress the data on the basis of the designated error range, transfer the data, and further display an error of each of the divided areas for each of the physical quantities on a receiver/client side.

This application provides an encoding method and an encoding apparatus based on a polar code, to improve compression performance of a source sequence of a limited length. The method includes: obtaining a source bit sequence; encoding the source bit sequence by using a polar code generation matrix that is based on sub-block column transformation, to obtain a first bit sequence, where the polar code generation matrix that is based on the sub-block column transformation is determined based on a first polar code generation matrix and a transformation matrix, and the transformation matrix may achieve effect of performing sub-block column transformation on the first polar code generation matrix; and compressing the first bit sequence, to obtain a compressed bit sequence.

The present disclosure relates to a method, a device, and related products for processing data. In an embodiment of the present disclosure, when processing data related to a neural network, an optimal truncation threshold value for a plurality of pieces of data is determined. The data is truncated through the truncation data threshold, and the plurality of pieces of data is quantized from a high-precision format to a low-precision format. The method in the present disclosure can ensure the precision of data processing as high as possible while reducing the amount of data processing. In addition, the method also helps to significantly reduce the amount of data transmission, thereby greatly accelerating the data exchange among a plurality of computing devices.

A compression engine may be designed for more efficient error checking of a compressed stream, to include adaptation of a heterogeneous design that includes interleaved hardware and software stages of compression and decompression. An output of a string matcher may be reversed to generate a bit stream, which is then compared with an input stream to the compression engine as a first error check. A final compressed output of the compression engine may be partially decompressed to reverse entropy code encoding of an entropy code encoder. The partially decompressed output may be compared with an output of an entropy code generator to perform a second error check. Finding an error at the first error check greatly reduces the latency of generating a fault or exception, as does performing computing-intensive aspects of the compression and decompression with software instead of specialized hardware.

Various embodiments for data compression by a processor. Levels of data distribution are configured for data processing, including a first level of the data distribution incorporating a GRID network of data storage nodes, and a second level of the data distribution incorporating a GRID network of compressive nodes in communication with the GRID network of data storage nodes. Input/output (I/O) for an associated storage volume is load balanced between the data storage nodes, as data passes through the first level into the second level to be compressed or uncompressed.