The present disclosure involves a hardware-supported 3D-stacked NVM data compression method and system, involving setting a first identifier to mark a compression state of written-back data, the method at least comprising steps of: dividing the written-back data into a plurality of sub-blocks and acquiring a plurality of first output results through OR operations among the sub-blocks, respectively, or acquiring a plurality of second output results through exclusive OR operations among the sub-blocks, and determining a compression strategy for the written-back data based on the first output results or the second output results; and setting a second identifier to mark a storing means of the written-back data so that the second identifier is in pair with the first identifier, and configuring a storage strategy for the written-back data that includes at least rotating the second identifier.

Certain aspects of the present disclosure relate to a wearable system including one or more wearable acquisition devices. Each acquisition device includes a sensor to capture samples of a biomedical signal and circuitry to process the samples for transmission to a mobile device. The samples are encoded for transmission and decoded at the mobile device to reconstruct the biomedical signal and, based on the reconstructed biomedical signal, provide output through a user interface of the mobile device. The wearable system includes at least an acquisition device for capturing an electro-cardiogram signal (ECG). Other biomedical signals, such as a photoplethysmograph (PPG) signal, may also be captured. The wearable system may comprise a Body Area Network (BAN).

Embodiments described herein provide systems and methods for sharing encoder output of video streams. In a particular embodiment, a method provides determining video profiles for each of a plurality of devices. The method further provides determining if two or more of the video profiles are similar by determining if parameters associated with each video profile differ by less than a threshold value. The method further provides transmitting a video stream encoded in a single format to the devices if they have similar profiles and transmitting video streams encoded in different formats to the devices if they do not have similar profiles.

A neural network acceleration device includes a processor and a storage medium. The storage medium stores instructions that, when executed by the processor, cause the processor to obtain an input feature value, perform computation processing on the input feature value to obtain an output feature value, and in response to a fixed-point format of the output feature value being different from a predetermined fixed-point format, perform at least one of a low bit shifting operation or a high bit truncation operation on the output feature value according to the predetermined fixed-point format to obtain a target output feature value. A fixed-point format of the target output feature value is the predetermined fixed-point format.

A communication system includes a processor and a memory that stores recovery bits of a previous message and instructions. The instructions cause the processor to, in response to receiving a new message, obtain the recovery bits of the previous message and selectively generate a candidate message by attempting recovery of the previous message from the new message and the recovery bits of the previous message. The instructions include, in response to an indicator indicating that the recovery was successful, computing a delta between the new message and the candidate message and generating a delivery message based on (i) the computed delta or, in response to the indicator indicating that the recovery was unsuccessful, (ii) the new message. The instructions include calculating new recovery bits from the new message, replacing the stored recovery bits of the previous message with the new recovery bits, and transmitting the delivery message to a destination.

Disclosed are techniques for encoding a set of sensor content symbols at least in part via applying a processing window of an adjustable size.

Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

A system for transmitting data over an optical communication path is configured to receive data to be encoded in a bitstream for transmission using an optical communication path and encodes the received data to obtain a bitstream. The system is further configured to determine that the bitstream includes a sequence of consecutive bits, and obtain a power level at which to transmit a portion of the bitstream based on a count of the consecutive bits in the sequence. The system may be configured to selectively activate a light source at a power level according to a modulation scheme to optically transmit the portion of the bitstream at the power level.

The present disclosure discloses example operation accelerators and compression methods. One example operation accelerator performs operations, including storing, in a first buffer, first input data. In a second buffer, weight data can be stored. A computation result is obtained by performing matrix multiplication on the first input data and the weight data by an operation circuit connected to the input buffer and the weight buffer. The computation result is compressed by a compression module to obtain compressed data. The compressed data can be stored into a memory outside the operation accelerator by a direct memory access controller (DMAC) connected to the compression module.