According to one embodiment, a data compression circuit includes a plurality of intermediate match candidate generation circuits. Each of the plurality of intermediate match candidate generation circuits generates an intermediate match candidate by incrementing, based on a match length received from a corresponding intermediate match candidate selection circuit, a match length corresponding to an intermediate match candidate generated in a previous cycle when a distance corresponding to the received match length matches a distance corresponding to the intermediate match candidate generated in the previous cycle and the received match length is greater than a threshold value.

In disclosed embodiments, compression circuitry may compress data blocks and compressed write data blocks and corresponding compression metadata to a certain level in a cache/memory hierarchy. In some embodiments, the compression circuitry is configured to detect a pre-determined set of data values in a block of data to be compressed. In response, the compression circuitry may write a special metadata value for the data block to data storage circuitry to indicate compression of the data block, without writing a compressed version of the data block to the data storage circuitry. This may advantageously improve performance and reduce power consumption for data blocks with certain data values (e.g., having uniform pixel/texel values).

Disclosed are a compressor for a memory device and an operating method thereof. a method of operating the compressor for the memory device includes: extracting first features from pages corresponding to application programs; clustering the first features into clusters, and generating cluster features respectively corresponding to the clusters; generating trees for compression, the trees respectively corresponding to the cluster features; and storing the trees for performing compression in the memory device.