Patent classifications
H03M7/6058
Data processing performance enhancement for neural networks using a virtualized data iterator
The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. Using virtualized hardware iterators, data for processing by the NN/DNN can be traversed and configured to optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, an iterator controller can generate instructions for execution by the NN/DNN representative of one more desired iterator operation types and to perform one or more iterator operations. Data can be iterated according to a selected iterator operation and communicated to one or more neuron processors of the NN/DD for processing and output to a destination memory. The iterator operations can be applied to various volumes of data (e.g., blobs) in parallel or multiple slices of the same volume.
Sparse dictionary tree
Techniques related to a sparse dictionary tree are disclosed. In some embodiments, computing device(s) execute instructions, which are stored on non-transitory storage media, for performing a method. The method comprises storing an encoding dictionary as a token-ordered tree comprising a first node and a second node, which are adjacent nodes. The token-ordered tree maps ordered tokens to ordered codes. The ordered tokens include a first token and a second token. The ordered codes include a first code and a second code, which are non-consecutive codes. The first node maps the first token to the first code. The second node maps the second token to the second code. The encoding dictionary is updated based on inserting a third node between the first node and the second node. The third node maps a third token to a third code that is greater than the first code and less than the second code.
Flexible hardware for high throughput vector dequantization with dynamic vector length and codebook size
The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as memory data management of a NN/DNN. Using vector quantization of neuron weight values, the processing of data by neurons can be optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, one or more contiguous segments of weight values can be converted into one or more vectors of arbitrary length and each of the one or more vectors can be assigned an index. The generated indexes can be stored in an exemplary vector quantization lookup table and retrieved by exemplary fast weight lookup hardware at run time on the flyas part of an exemplary data processing function of the NN as part of an inline de-quantization operation to obtain needed one or more neuron weight values.
ACCELERATING MEMORY COMPRESSION OF A PHYSICALLY SCATTERED BUFFER
Embodiments herein describe using compression engines in a processor subsystem to compress only the data fragments stored locally. That is, an application may be allocated a buffer where the physical memory of that buffer is spread across multiple processor subsystems. Rather than asking a single actor (e.g., a single host processor or compression engine) to compress all the fragments of the buffer, a compression library can instead instruct the individual compression engines in each of the processor subsystems to compress only the fragments stored in local memory in the same processor subsystem. Doing so leverages the memory affinity between the compression engines in the local memory which can reduce the overall time required to perform compression.
Parallel Lempel-Ziv compression for highly-parallel computer architectures
One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.
Processing discontiguous memory as contiguous memory to improve performance of a neural network environment
The performance of a neural network (NN) can be limited by the number of operations being performed. Using a line buffer that is directed to shift a memory block by a selected shift stride for cooperating neurons, data that is operatively residing memory and which would require multiple write cycles into a cooperating line buffer can be processed as in a single line buffer write cycle thereby enhancing the performance of a NN/DNN. A controller and/or iterator can generate one or more instructions having the memory block shifting values for communication to the line buffer. The shifting values can be calculated using various characteristics of the input data as well as the NN/DNN inclusive of the data dimensions. The line buffer can read data for processing, shift the data of the memory block and write the data in the line buffer for subsequent processing.
Electronic device and method for compressing sampled data
An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.
Electronic device and method for compressing sampled data
An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, PROGRAM, AND INFORMATION PROCESSING METHOD
[Object] To provide an information processing apparatus, an information processing system, a program, and an information processing method that are capable of executing decoding without necessity of a large memory resource.
[Solving Means] An information processing apparatus according to the present technology includes a decoder. The decoder acquires a top position of each piece of data of a plurality of channels included in each frame of compressed audio data and decodes the data of the plurality of channels for each block with a predetermined size from the top position.
METHOD AND DEVICE FOR STORING TIME SERIES DATA WITH ADAPTIVE LENGTH ENCODING
Provided are a method and device for storing time series data with adaptive length encoding, including: acquiring data values corresponding to timestamps according to a sequential order of timestamps; using a ratio of storage space values required to pre-store the previous n data values to storage space values required to pre-store rule information of a preset encoding rule and encoding data according to the previous n data values as a storage gain corresponding to the time at which the n-th data value is acquired; storing the rule information of the preset encoding rule and the encoding data corresponding to a previous n1 data values when the storage gain corresponding to the time at which the n-th data value is acquired is less than that corresponding to the time at which the (n1)-th data value is acquired.