H03M7/6058

Configurable compression circuit

A compression circuit includes a buffer, a selection circuit, a compare circuit, and a control circuit. The buffer stores uncompressed data. The selection circuit generates a read pointer value to the buffer. The control circuit contains a programmable configuration register. The configuration register stores a depth value for reading uncompressed data from the history buffer. The control circuit generates control signals to the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value. Responsive to the second value corresponding to the depth value, the control circuit resets the read pointer value to the initial value. The compare circuit compares input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.

PARALLEL LEMPEL-ZIV COMPRESSION FOR HIGHLY-PARALLEL COMPUTER ARCHITECTURES
20190288706 · 2019-09-19 ·

One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.

Parallel Lempel-Ziv compression for highly-parallel computer architectures

One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.

Compression hardware including active compression parameters

A computer system includes a host system that runs an application. The application outputs a compression request to compress a data stream having an initial data-representation size, and which includes a plurality of individual data chunks. A hardware controller compresses the plurality of individual data chunks according to different encodings based on a compression ratio of each of the individual data chunks to generate a compressed data stream having a reduced data-representation size with respect to the initial data-representation size.

Data recovery utilizing optimized code table signaling
10361716 · 2019-07-23 · ·

A computer-implemented method, system, and apparatus for storing binary data is disclosed. A processor receives a digital bit stream and transforms the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises a data message encoded by an OCTS-expanded table for storage. The processor stores the encoded digital bit stream on a digital data storage device or system.

Storage device and operating method of the storage device

A memory device may include a data receiver configured to receive a plurality of read data chunks from a plurality of memory areas which transmit and receive data through one channel, a data compressor configured to generate a plurality of compressed data chunks from each of the plurality of read data chunks and a data output unit configured to simultaneously output the plurality of compressed data through the channel in response to a data output command.

Dictionary compression device and memory system

According to one embodiment, a dictionary buffer stores dictionary data including a first substring and data before the first substring. A substring generator generates, from second input data, second substrings. A transformer transforms each of the second substrings into a hash value. A read processor reads the dictionary data, using a hash value transformed from a third substring among the second substrings. An acquisition unit compares a data string including the third substring and data before the third substring with the read dictionary data, and acquire first and second match lengths of the third and fourth substrings. A coded data generator generates coded data based on the acquired first and second match lengths.

SPARSE DICTIONARY TREE

Techniques related to a sparse dictionary tree are disclosed. In some embodiments, computing device(s) execute instructions, which are stored on non-transitory storage media, for performing a method. The method comprises storing an encoding dictionary as a token-ordered tree comprising a first node and a second node, which are adjacent nodes. The token-ordered tree maps ordered tokens to ordered codes. The ordered tokens include a first token and a second token. The ordered codes include a first code and a second code, which are non-consecutive codes. The first node maps the first token to the first code. The second node maps the second token to the second code. The encoding dictionary is updated based on inserting a third node between the first node and the second node. The third node maps a third token to a third code that is greater than the first code and less than the second code.

Storage device and operating method of the storage device

A storage device may include: a memory device for extracting bits having a first logic value among bits included in data received from outside the memory device, generating a plurality of compressed data chunks including the bits comprising the first logic value and position information representing positions of the bits having the first logic value in the data, and outputting the plurality of compressed data chunks in response to a data output command; and a memory controller for receiving the plurality of compressed data chunks from the memory device, and recovering the data, based on the bits having the first logic value, which are included in the plurality of compressed data, and the position information.

Compressing probability tables for entropy coding
12034462 · 2024-07-09 · ·

This disclosure provides methods, devices, and systems for data compression. The present implementations more specifically relate to encoding techniques for compressing probability tables used for entropy coding. In some aspects, an entropy encoder may encode a probability table so that one or more contexts are represented by fewer bits than would otherwise be needed to represent the frequency of each symbol as a proportion of the total frequency of all symbols associated with such contexts. For example, if a given row of the probability table (prior to encoding) includes a number (M) of entries each having a binary value represented by a number (K) of bits, the same row of entries may be represented by fewer than M*K bits in the encoded probability table.