Consistent with a further aspect of the present disclosure, previously encoded data is stored in a memory, and an encoder accesses both input data and previously encoded data to generate new encoded data or a new codeword. Each codeword is stored in a row of the memory, and with each newly generated codeword, each previously stored code word is shifted to an adjacent row of the memory. In one example, the memory is delineated as a plurality of blocks including rows and columns of bits. When generating a new code word, randomly selected columns of bits in the memory are read from randomly selected blocks of the memory and supplied to the encoder. In this manner the number of times the memory is access is reduced and power consumption is reduced.

A method and apparatus for a CTC data copy operation, in that modification, and subsequent encoding only affects a small portion of metadata associated with copied data. By modifying and re-encoding only this small portion of metadata, a small portion of the parity data for the copied data requires updating. In embodiments where there are no errors in the read data to be copied (e.g., from an SLC portion of a NAND), decoding, modification, and encoding, may be done in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits may be predetermined and combined (e.g., by XOR) to update the metadata parity bits.

A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

A method of telecommunications includes the steps of receiving an encoded block having a plurality of values, dividing the received encoded block into a plurality of received segments, each received segment comprising at least two of the values, decoding each received segment by providing, for each received segment, a plurality of estimated encoded sequences, each estimated encoded sequence comprising at least two data units, merging estimated encoded sequences for consecutive segments to provide a plurality of candidate sequences, and selecting one of the plurality of candidate sequences by performing a closest fit calculation between the received encoded data block and each of the candidate sequences. The method is suitable for use in software-defined radios.

A systematic encoder reliably transferring a source data block (SDB) is configured for an outer transform matrix and an inner transform matrix. An inner encoder receives the SDB and generates an output constraint block (OCB) as an SDB image under an inverse of a submatrix of the inner transform matrix. An outer encoder receives a fixed data block (FDB) and the OCB and generates a transform output block (TOB) as a transform input block (TIB) image under the outer transform matrix. The TIB contains the FDB transparently in a sub-block of the TIB, and the TOB contains the OCB transparently in a sub-block of the TOB. The inner encoder receives the TOB and generates a transmitted code block (TCB), transparently containing the SDB in a sub-block therein.

A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

Devices, systems and methods for convolutional precoding and decoding of polar codes are disclosed. An example method for error correction in a data processing system includes receiving a noisy codeword, the codeword having been generated based on an outer stream decodable code and an inner polar code and provided to a communication channel or a storage channel prior to reception by the decoder, the stream decodable code characterized by a trellis, and performing, based on the trellis, a list-decoding operation on the noisy codeword vector to generate a plurality of information symbols, the list-decoding operation being configured to traverse through a plurality of states at one or more stages of a plurality of decoding stages.

Various implementations described herein relate to correcting errors in Dynamic Random Access Memory (DRAM). A memory controller uses an Error Correcting Code (ECC) to store an encoded data word within a DRAM die. The DRAM die is communicatively coupled the memory controller by a memory data bus. The DRAM die includes on-die error correction for data bits stored in the DRAM. Upon reading the encoded data word, the memory controller corrects and detects one or more errors. The one or more errors are introduced by at least one of the on-die error correction of the DRAM die or the memory data bus.

A systematic encoder reliably transferring a source data block (SDB) is configured for an outer transform matrix and an inner transform matrix. An inner encoder receives the SDB and generates an output constraint block (OCB) as an SDB image under an inverse of a submatrix of the inner transform matrix. An outer encoder receives a fixed data block (FDB) and the OCB and generates a transform output block (TOB) as a transform input block (TIB) image under the outer transform matrix. The TIB contains the FDB transparently in a sub-block of the TIB, and the TOB contains the OCB transparently in a sub-block of the TOB. The inner encoder receives the TOB and generates a transmitted code block (TCB), transparently containing the SDB in a sub-block therein.