A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, the apparatus is configured to determine a number of data symbols for transmitting a data payload. The apparatus is configured to determine a number of payload bits for transmitting the data payload based on the determined number of data symbols. The apparatus is configured to transmit a data frame. The data frame includes a signal field and data symbols encoded based on the data payload, the determined number of data symbols, and the determined number of payload bits, in which the data symbols are encoded using LDPC encoding or BCC encoding.

A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, the apparatus is configured to determine a number of data symbols for transmitting a data payload. The apparatus is configured to determine a number of payload bits for transmitting the data payload based on the determined number of data symbols. The apparatus is configured to transmit a data frame. The data frame includes a signal field and data symbols encoded based on the data payload, the determined number of data symbols, and the determined number of payload bits, in which the data symbols are encoded using LDPC encoding or BCC encoding.

Error-correcting performance of polarization-adjusted convolutional codes is improved by refreezing low weight indices. For information bits (k), where k is a positive integer, a plurality of convolutionally encoded bits (n) are generated by performing a convolutional encoding operation on the plurality of information bits and a plurality of frozen bits (nk), where n is a positive integer. A refreezing operation is performed on the convolutionally encoded bits, including dynamically assigning zeros to selected frozen indices such that a number of low weight codewords is reduced. Polar encoded bits are generated by performing a polar encoding operation on an output of the refreezing operation, providing polar encoded bits for transmission or storage.

A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

Techniques to increase the capacity of a W-CDMA wireless communications system. In an exemplary embodiment, early termination of one or more transport channels on a W-CDMA wireless communications link is provided. In particular, early decoding is performed on slots as they are received over the air, and techniques are described for signaling acknowledgment messages (ACK's) for one or more transport channels correctly decoded to terminate the transmission of those transport channels. The techniques may be applied to the transmission of voice signals using the adaptive multi-rate (AMR) codec. Further exemplary embodiments describe aspects to reduce the transmission power and rate of power control commands sent over the air, as well as aspects for applying tail-biting convolutional codes in the system.

Techniques to increase the capacity of a W-CDMA wireless communications system. In an exemplary embodiment, early termination (400) of one or more transport channels on a W-CDMA wireless communications link is provided. In particular, early decoding (421, 423) is performed on slots as they are received over the air, and techniques are described for signaling (431, 432) acknowledgment messages (ACK's) for one or more transport channels correctly decoded to terminate the transmission of those transport channels. The techniques may be applied to the transmission of voice signals using the adaptive multi-rate (AMR) codec. Further exemplary embodiments describe aspects to reduce the transmission power and rate of power control commands sent over the air, as well as aspects for applying tail-biting convolutional codes (1015) in the system.

A non-systematic convolutional decoder of a convolutionally encoded multi-level data stream includes a shift register and two or more paths of exclusive-OR (XOR) gates, arranged to reconstruct an original input information stream, each path having a quantiser arranged to quantise the signal to two levels, and a set of XOR gates arranged to match an encoding path in an associated convolutional encoder, and a selector arranged to feed an output from each path to a single input of the shift register. If the paths have differing values at their output, the selector may choose the value from the path based upon a function of the multi-level signals associated with each path, such as the path with the largest absolute signal level. The decoder provides a simple means for decoding signals while allowing the signal to also or instead be decoded using e.g. a Viterbi decoder if higher performance is required.

A method for encoding bits according to a convolutional code. Bits to be encoded with the convolutional code are obtained for transmission over a communication channel. The bits are encoded according to the convolutional code with an encoder having an M-bit memory and a plurality of logic gates so as to separate trellis segments of the convolutional code into trellis sub-segments having a reduced number of branches per state than that of the trellis segments.

A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to 0 and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a determined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the determined column among one or more column(s) of the parity check matrix.

System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two.