A data processing method and a data processing apparatus are provided to reduce a bit error rate of a wireless communications system and improve transmission performance of the wireless communications system. The method includes: mapping L to-be-sent bits to L bit locations included in at least one modulation symbol, where the L to-be-sent bits include at least one bit field, a bit in a bit field having a high priority is preferentially mapped to a bit location that is of the at least one modulation symbol and that has a high reliability level, the at least one bit field is at least one of an information bit field, a first parity bit field, and a second parity bit field; and outputting the at least one modulation symbol.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter may determine a first modulation order for a first layer of a communication and a second modulation order for a second layer of the communication, wherein the first modulation order and the second modulation order are different; interleave bits for one or more of the first layer or the second layer based at least in part on the first modulation order and the second modulation order; and transmit the interleaved bits via the one or more of the first layer or the second layer. Numerous other aspects are provided.

The present invention is directed to communication systems and methods. According to a specific embodiment, FEC data streams from multiple FEC data lanes are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. A second stage interleaving process is performed to interleave the inner encoded data streams. There are other embodiments as well.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may select, for a communication on a multi-slot transmission occasion, coded bits of a plurality of coded bits on a per slot basis, for each of multiple slots of the multi-slot transmission occasion. The UE may interleave the coded bits on a per slot basis to form one or more interleaved encoded bit sequences of a codeblock. The UE may transmit the communication including the one or more interleaved encoded bit sequences. Numerous other aspects are provided.

An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a repeater configured to repeat, in the LDPC codeword, at least some bits of the LDPC codeword in the LDPC codeword so that the repeated bits are to be transmitted in the current frame; a puncturer configured to puncture some of the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits, and generate additional parity bits to be transmitted in a previous frame of the current frame.