Patent classifications
H03M13/271
SYSTEM, METHOD, AND APPARATUS FOR INTERLEAVING DATA
A method, system, and apparatus for interleaving data including creating a buffer, writing input data, and reading output data out of the buffer.
Turbo product polar coding with hard decision cleaning
An encoder for encoding source information into an encoded codeword used in a communication channel includes a data input to receive source data, a processor, and a memory to store an encoder program. The encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, and the TPC structure comprises a data block corresponding to the source data, a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, and a second parity block having a row parity block, a joint parity block and a column parity block.
PARALLEL BIT INTERLEAVER
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.
Parallel bit interleaver
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.
Time varying data permutation apparatus and methods
Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
Data processing device and data processing method for improving data transmission quality using a low density parity check code
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.
Data processing device and data processing method
A transmitting device for generating a digital television broadcast signal incudes circuitry configured to receive data to be transmitted in a digital television broadcast signal and perform LDPC (low density parity check) encoding on input bits of the received data according to a parity check matrix initial value table of an LDPC code having a code length of 16200 bits and a code rate of 10/15 to generate an LDPC code word. The LDPC code enables error correction processing to correct errors generated in a transmission path of the digital television broadcast signal. The LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors.
Transmitting apparatus and interleaving method thereof
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
Error correction device and error correction method
Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems.