A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Consistent with a further aspect of the present disclosure, previously encoded data is stored in a memory, and an encoder accesses both input data and previously encoded data to generate new encoded data or a new codeword. Each codeword is stored in a row of the memory, and with each newly generated codeword, each previously stored code word is shifted to an adjacent row of the memory. In one example, the memory is delineated as a plurality of blocks including rows and columns of bits. When generating a new code word, randomly selected columns of bits in the memory are read from randomly selected blocks of the memory and supplied to the encoder. In this manner the number of times the memory is access is reduced and power consumption is reduced.

Method and system method performed at a wireless transmitting station, including generating a first low density parity check (LPDC) codeword for a first source word for a first transmission, and generating a second LDPC codeword for a retransmission for the first LDPC codeword, the second LDPC codeword including a permutated subset of information bits included in the first LDPC codeword and parity check bits corresponding to the permutated subset of information bits.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code.

A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2.