Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

A decoding method and device for Turbo product codes, a decoding device, a decoder and a computer storage medium are provided. The method includes: a received codeword of a Turbo product code is acquired, and iterative decoding is performed on the received codeword for a set first iterative decoding times (S101); a decoding result of iterative decoding performed for the first iteration times is judged according to a first decoding rule to obtain a decoding identifier representing the decoding result (S102); and error correction processing is performed on the Turbo product code on which iterative decoding is performed for the first iteration times according to the decoding identifier (S103).

A system, method and program product that utilizes a hybrid fault tolerance system for managing data. A system is disclosed that includes: a system for partitioning memory into a set of partitions that includes a designated partition for storing immutable objects; a write system for storing an immutable object in the designated partition, wherein the immutable object is coded with a hardware-based fault tolerance system to generate a set of hardware-based codewords, and wherein the immutable object is further coded with a software-based fault tolerance system to generate a set of software-based codewords; a read system for retrieving the immutable object, wherein the read system decodes each hardware-based codeword for the immutable object, and in response to a failed decoding of a hardware-based codeword, the read system decodes the software-based codeword containing a failed hardware-based codeword.

A method for hierarchical correction coding includes converting data for a storage system into w storage device arrays, each storage device array including n storage devices, and each storage device divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Erasures in the w storage device arrays are corrected based on protecting each row and column in each m×n array by an erasure-correcting code. Each group of t storage devices contains extra parities to correct extra erasures in addition to erasures corrected by vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.

In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A,114B), LDPC encoded data formed by LDPC encoding blocks (102A,102B). In a case of a retransmittal, the multi-antenna transmitting apparatus (100) uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (114A).

A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.

Multi-dimensional parity checker (MDPC) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the MDPC system includes a control register and a parity checker. The parity checker receives data segments accessed from the data region. The parity checker generates and accumulates multi-dimensional parity bits for the data segments and subsequently compares accumulated bits to expected multi-dimensional parity bits to generate multi-dimensional error syndrome bits representing identified comparison errors. The parity checker also determines a syndrome state based upon the multi-dimensional syndrome bits and stores the syndrome state within the control register. The parity checker operates in different modes based upon different values stored in an operational mode field of the control register. The parity checker can operate in a real-time error correction mode to correct errors within the data region from subsequent random accesses by components within the integrated circuit.

In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.