In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks B.sub.i, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block B.sub.i in the sequence are computed. The coding symbols are computed such that, for each symbol block B.sub.i that has a preceding symbol block B.sub.i1 and a subsequent symbol block B.sub.i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B.sub.i1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol B.sub.i, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol B.sub.i, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B.sub.i+1, form a codeword of the FEC component code. Thus, each row in [B.sub.i1.sup.T B.sub.i] and each column in $\left[\begin{array}{c}{B}_i\\ B_{i+1}^T\end{array}\right],$
for example, is a valid codeword.

A receiver includes a polar decoder for decoding an encoded codeword transmitted over a communication channel. The receiver includes a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel and a soft decoder operated by a processor to produce a soft output of the decoding. The codeword is encoded by at least one polar encoder with a polar code. The processor is configured to estimate possible values of the bits of the received codeword using a successive cancelation list (SCL) decoding to produce a set of candidate codewords, determine a distance between each candidate codeword and a soft input to the soft decoder, and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

A transmitter for transmitting an encoded codeword over a communication channel is described. The transmitter includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce an encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel, wherein the polar code is specified by a set of regular parameters and a set of irregular parameters.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.

Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.

An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

A method of reading an optical code (20) is provided that has a plurality of code words, wherein image data having the optical code (20) are recorded and evaluated to read out the code words, and wherein it is determined by a test process whether the code is read correctly. In this respect, a code word at at least one position of the code (20) is replaced with a code word known for this position in a pre-correction and the test process is carried out after the pre-correction.

Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.