A memory system (e.g., a solid state drive, or SSD) uses application-aware ECC schemes to make use of the specifics of a database schema and analytic queries. Only the fields relevant to the query are decoded, other fields are largely ignored. Integrated interleaved (II) codes and product codes approaches are described. Compared to traditional ECC schemes that decode the entire records before any fields to be used by the analytics are available, the new application-aware ECC schemes may achieve orders of magnitudes throughput improvement and/or substantially lower decoder complexity.

Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

A hybrid type iterative decoding method for a three-dimensional turbo product code (TPC) having a first axis (FA), a second axis (SA), and a third axis (TA) including: a parallel decoding step of applying a predetermined decoding algorithm (PDA) in parallel to current FA and SA input values (IVs) which are determined based on at least two previous decoding values (DVs), respectively, among the previous FA, SA and TA DVs which are generated in advance to generate a current FA DV and a current SA DV, respectively; a serial decoding step of applying PDA to a current TA IV determined based on the current FA and SA DVs to generate a current TA DV; and performing hard decision based on the current FAs DV, the current SA DV, the current TA DV, and the received signal value.

An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

Disclosed is a three-dimensional TPC decoding apparatus. A three-dimensional TPC decoding apparatus includes an X decoder which decodes an X axis of an m-th upper half layer based on decoding results of a Y axis and a Z axis of an m1-th upper half layer; a Y decoder which decodes a Y axis of an m-th lower half layer based on decoding results of an X axis and a Z axis of an m1-th lower half layer; and a Z decoder which decodes a Z axis based on a decoding result of the Y axis of an m-th upper half layer and a decoding result of the X axis of an m-th lower half layer.

Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

A method of processing broadcast data in a broadcast transmitting system, the method includes randomizing, by a hardware processor, the broadcast data; first encoding, by the hardware processor, the randomized broadcast data to add first parity data for first forward error correction; second encoding, by the hardware processor, the first-encoded broadcast data to add second parity data for second forward error correction; permuting the second-encoded broadcast data; block interleaving, by the hardware processor, the permuted broadcast data; third encoding signaling information for signaling the broadcast data to add parity data; fourth encoding the third-encoded signaling information at a code rate; block interleaving the fourth-encoded signaling information; modulating the block-interleaved broadcast data and the block-interleaved signaling information; and transmitting a broadcast signal including the modulated broadcast data and the modulated signaling information.