In a Forward Error Correction (FEC) technique, parity vectors are computed such that: each parity vector spans a set of frames; a subset of bits of each frame is associated with parity bits in each parity vector; and a location of parity bits associated with one frame in one parity vector is different from that of parity bits associated with the frame in another parity vector. Values of decoded bits of a first frame are deduced from known parity bits of a first parity vector having an effective length of one frame. For parity vectors having, an effective length greater than one frame, a Log Likelihood Ratio of each unknown parity bit associated with the first frame is updated based on known and unknown parity bits of each parity vector. The first frame is decoded using the deduced bit values and the updated LLR values.

Embodiments relate to decoding data read from a non-volatile storage device, including determining error candidates for the data based on component codes, determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate, determining whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate in response to implementing a suggested correction at one of the error candidates, and correcting errors in the data based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.