A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

Provided is a method for decoding a staircase code. The method includes following steps: soft information updating is performed on S initial encoding blocks in a staircase code to obtain a first information block, and last S−T encoding blocks in the first information block and T newly-added encoding blocks are updated to obtain a second information block; decoding is performed on first T encoding blocks in the first information block and first S−T encoding blocks in the second information block to obtain a third information block; and following operations are repeatedly performed: S−T information blocks are selected, the soft information updating is performed to obtain S updated information blocks, and the S updated information blocks are used as a new second information block; and decoding is performed to obtain a new third information block, and information of first T blocks is outputted as the output of the decoder.

A method includes: obtaining a first sequence, where the first sequence includes T first subsequences; determining T encoding vectors based on the T first subsequences; generating T second subsequences based on one or more codebooks and the T encoding vectors, where each first subsequence corresponds to one column vector group in the one or more codebooks, and a column vector group corresponding to at least one of the T first subsequences includes at least two column vectors; and sending the T second subsequences.

Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately.

Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately.

There is provided a decoding circuit including; a first decoding unit that decodes a first signal from a multiplexed signal in which the first signal and a second signal are multiplexed in an LDM (Layered Division Multiplexing) system; and a second decoding unit that decodes the second signal from the multiplexed signal using the decoding result of the decoded first signal, wherein the second signal is selectively decoded based on noise information related to a reception state of the multiplexed signal.

An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y−Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

In this invention, a novel method for improving the performance of polar decoders using virtual random channels is proposed.

This application discloses example decoding methods, example decoders, and example decoding apparatuses. One example decoding method includes performing soft decision decoding on a first sub-codeword in a plurality of sub-codewords to obtain a hard decision result. It is determined whether to skip a decoding iteration. In response to determining not to skip the decoding iteration, a first turn-off identifier corresponding to the first sub-codeword is set to a first value based on the hard decision result. The first turn-off identifier indicates whether to perform soft decision decoding on the first sub-codeword in a next decoding iteration. The soft decision decoding is not performed on the first sub-codeword in the next decoding iteration when a value indicated by the first turn-off identifier is the first value. The hard decision result is stored.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.