Patent classifications
H03M13/2951
REDUCING A DECODING ERROR FLOOR BY POST-PROCESSING CODEWORDS ENCODED BY BINARY SYMMETRY-INVARIANT PRODUCT CODES
A decoder performs iterative decoding of a codeword encoded by a binary symmetry-invariant product code, such as a half product code or quarter product code. In response to the iterative decoding reaching a stopping set, the decoder determines by reference to an ambient error graph formed from the stopping set whether or not the stopping set is correctable by post-processing. If not, the decoder outputs the uncorrected codeword and signals a decoding failure. In response to determining that the stopping set is correctable by post-processing, the decoder inverts all bits of the codeword corresponding to edges of the ambient error graph, applies an additional round of iterative decoding to the codeword to obtain a corrected codeword, and outputs the corrected codeword. Post-processing in this manner substantially lowers an error floor associated with the binary symmetry-invariant product code.
APPARATUSES AND METHODS FOR STAIRCASE CODE ENCODING AND DECODING FOR STORAGE DEVICES
An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.
SYSTEM AND METHOD FOR ADAPTIVE MULTIPLE READ OF NAND FLASH
A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.
DECODING OF PRODUCT CODES
In one embodiment, a method includes receiving data and in an iterative process until decoded data is output or a predetermined number of full iterations have occurred: C1 decoding all first subsets of the data, determining whether to stop decoding the data after the C1 decoding, incrementing a half iteration counter to indicate completion of a half iteration, C2 decoding all second subsets of the data two or more times in each half iteration using two or more C2-decoding methods in response to a determination that a second subset is not decoded successfully using a first C2-decoding method, determining whether to stop decoding the data after the C2 decoding, incrementing the half iteration counter to indicate completion of another half iteration, and outputting the set of decoded data in response to a determination that all subsets of the data are decoded successfully.
Decoding of product codes
In one embodiment, a method for decoding data includes iteratively C1 decoding all first subsets of a set of data two or more times in each half iteration using two or more C1-decoding methods when a first subset is not decoded successfully using a first C1 decoding, determining whether to stop decoding the set of data after the C1 decoding and output results of the C1 decoding, incrementing a half iteration counter to indicate completion of a half iteration in response to decoding not being stopped, C2 decoding all second subsets of the set of data, determining whether to stop decoding the set of data after the C2 decoding and output results of the C2 decoding, incrementing the half iteration counter to indicate completion of another half iteration in response to decoding not being stopped, and outputting decoded data when all subsets of the set of data are decoded successfully.
METHODS AND APPARATUS FOR ERROR CORRECTION CODING INTEGRATED WITH TRANSMISSION DIVERSITY
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The present disclosure discloses a method and an apparatus for error correction coding in a communication system, more specifically, to error correction coding integrated with transmission diversity.