In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

A method, system, and non-transitory computer-readable recording medium of decoding a signal are provided. The method includes receiving signal to be decoded, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining magnitudes of the LLRs; identifying K bits of the signal with smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords; and stopping after a first candidate codeword passes the CRC.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

A decoding method performed by a receive end device is disclosed. The decoding method includes: receiving a first bit signal; performing level-M forward error correction (FEC) decoding on the first bit signal to obtain a second bit signal, where M is a positive integer greater than zero; checking the second bit signal to obtain a first check result; performing level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and, upon determining that M+1 reaches a first preset threshold, performing data processing on the third bit signal to obtain a fourth bit signal, where the fourth bit signal is used by the receive end device to obtain service data transmitted by a transmit end device.

Method for decoding signal includes receiving signal, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) for each at least one bit at each stage is determined, and identified in vector L.sub.APP; performing Cyclic Redundancy Check (CRC) on L.sub.APP, and stopping if L.sub.APP passes CRC; otherwise, determining magnitudes of LLRs in L.sub.APP; identifying K LLRs in L.sub.APP with smallest magnitudes and indexing K LLRs as r={r(1), r(2), . . . , r(K)}; setting L.sub.max to maximum magnitude of LLRs in L.sub.APP or maximum possible LLR quantization value; setting v=1; generating {tilde over (L)}.sub.A(r(k))=L.sub.A(r(k))L.sub.maxv.sub.ksign[L.sub.APP(r(k))], for k=1, 2, . . . , K; decoding with {tilde over (L)}.sub.A to identify {tilde over (L)}.sub.APP, wherein {tilde over (L)}.sub.APP is LLR vector; and performing CRC on {tilde over (L)}.sub.APP, and stopping if {tilde over (L)}.sub.APP passes CRC or v=2.sup.K-1; otherwise, incrementing v and returning to generating {tilde over (L)}.sub.A(r(k)).

A deep neural network (DNN) media noise predictor configured for one-dimensional-magnetic (1DMR) recording or two-dimensional-magnetic (TDMR) is introduced. Such architectures are often combined with a trellis-based intersymbol interference (ISI) detection component in a turbo architecture to avoid the state explosion problem by separating the inter-symbol interference (ISI) detection and media noise estimation into two separate detectors and uses the turbo-principle to exchange information between them so as to address the modeling problem by way of training a DNN-based media noise estimators. Thus, beneficial aspects include a reduced bit-error rate (BER), an increased areal density, and a reduction in computational complexity and computational time.

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

A method is performed by an information decoder. The method comprises obtaining (S102) an encoded sequence having been encoded using a polar code. The method comprises successively decoding (S104) the encoded sequence into the successive bits of the decoded sequence. Successively decoding the encoded sequence comprises performing a threshold check (S106) for evaluating a bit uncertainty criterion. Successively decoding the encoded sequence comprises branching (S108) the decoded sequence into two candidate decoded sequences whenever the threshold check fails.