Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.

A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.

A method for encoding bits according to a convolutional code. Bits to be encoded with the convolutional code are obtained for transmission over a communication channel. The bits are encoded according to the convolutional code with an encoder having an M-bit memory and a plurality of logic gates so as to separate trellis segments of the convolutional code into trellis sub-segments having a reduced number of branches per state than that of the trellis segments.

The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p1), m(p2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output.

A method, system, and computer program product for performing robust, parallel data transfer by a processor device. Data is segmented into k-bit segments, where k1. The k-bit segments are convolution encoded, using m1 stages of delay. The n output streams are transmitted in parallel for increased effective data rate, where n>k. The n output streams are received. An XOR (Exclusive OR) logic is applied to the n output streams with pathing allowed by the convolution encoding, in a trellis-decoding diagram.

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits and a target constraints vector, placing the information bits in an input vector, setting balance bits included in the input vector to zero, encoding the input vector using a systematic code to obtain a preliminary codeword, applying a constraints matrix to the preliminary codeword to obtain a preliminary constraints vector, applying a transition matrix to a sum of the preliminary constraints vector and the target constraints vector to determine updated balance bits, obtaining an output codeword based on the information bits and the updated balance bits, and storing the output codeword in the storage device.