Patent classifications
H03M13/3972
Parallel turbo decoding with non-uniform window sizes
A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.
Telecommunications method
A method of telecommunications includes the steps of receiving an encoded block having a plurality of values, dividing the received encoded block into a plurality of received segments, each received segment comprising at least two of the values, decoding each received segment by providing, for each received segment, a plurality of estimated encoded sequences, each estimated encoded sequence comprising at least two data units, merging estimated encoded sequences for consecutive segments to provide a plurality of candidate sequences, and selecting one of the plurality of candidate sequences by performing a closest fit calculation between the received encoded data block and each of the candidate sequences. The method is suitable for use in software-defined radios.
METHODS AND SYSTEMS FOR MANAGING DECODING OF CONTROL CHANNELS ON A MULTI-SIM UE
Methods and systems for managing decoding of control channel on a multi-SIM UE. A method includes receiving, by the UE, the plurality of control channels from at least one Base Station (BS), the plurality of control channels corresponding to a plurality of Subscriber Identity Modules (SIMs), selecting, by the UE, a respective decoder for each of the plurality of SIMS, and decoding, by the UE, each respective control channel among the plurality of control channels using the respective decoder for a respective SIM among the plurality of SIMS, the respective SIM corresponding to the respective control channel.
Deep Learning for Behavior-Based, Invisible Multi-Factor Authentication
Biometric behavior-based authentication may be enhanced by using convolutional deep neural networks to learn subject-specific features for each subject. The advantage is two-fold. First the need for a domain expert is eliminated, and the search space can be algorithmically explored. Second, the features that allow each subject to be differentiated from other subjects may be used. This allows the algorithm to learn the aspects of each subject that make them unique, rather than taking a set of fixed aspects and learning how those aspects are differentiated across subjects. The combined result is a far more effective authentication in terms of reduction of errors. Behavior-based, invisible multi-factor authentication (BIMFA) mays also automate the responses to authentication second and third factor requests (something you have and something you are). BIMFA leverages continuous, invisible behavioral biometrics on user devices to gain a continuous estimate of the authorization state of the user across multiple devices without requiring any explicit user interaction or input for authentication. As a result, BIMFA can demonstrate that a device is under the control of the authorized user without requiring any direct user interaction.
SC-LDPC code encoding method and device therefor
Disclosed is an encoding method of a spatially coupled-low density parity Check (SC-LDPC) code of a terminal. The encoding method of the SC-LDPC code of the present disclosure can comprise: a step of generating a plurality of decomposition matrices by decomposing a base matrix of a preset LDPC block code. a step of generating a base matrix of the SC-LDPC code by spatially coupling the plurality of decomposition matrices in accordance with the termination length. a step of generating a circulant shift value matrix from the base matrix of the SC-LDPC code. a step of generating a plurality of lifting values for the base matrix of the SC-LDPC code. and a step for encoding an input signal by using a generator matrix defined by using of the base matrix of the SC-LDPC code, the circulant shift value matrix, and the plurality of lifting values.
Content aware decoding method and system
A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.
METHODS AND DEVICES FOR RATE ADAPTIVE FORWARD ERROR CORRECTION USING A FLEXIBLE IRREGULAR ERROR CORRECTING CODE
Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes.
Methods and devices for rate adaptive forward error correction using a flexible irregular error correcting code
Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes.
Hybrid data reduction
An information handling system may include at least one processor and a memory coupled to the at least one processor. The information handling system may be configured to receive data comprising a plurality of data chunks; perform deduplication on the plurality of data chunks to produce a plurality of unique data chunks; determine a compression ratio for respective pairs of the unique data chunks; determine a desired compression order for the plurality of unique data chunks based on the compression ratios; combine the plurality of unique data chunks in the desired compression order; and perform data compression on the combined plurality of unique data chunks.
Error correction decoding device and optical transmission/reception device
Provided is an optical transmission/reception device including an error correction decoding unit (36) for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit (36) is configured to perform decoding processing using a parity check matrix (70) of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices (71) combined with each other, in which the decoding processing is windowed decoding processing that uses a window (80) over one or more parity check sub-matrices (71), and in which a window size of the window (80) and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit (12) connected to the error correction decoding device (36).