A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

A method is performed by an information decoder. The method comprises obtaining (S102) an encoded sequence having been encoded using a polar code. The method comprises successively decoding (S104) the encoded sequence into the successive bits of the decoded sequence. Successively decoding the encoded sequence comprises performing a threshold check (S106) for evaluating a bit uncertainty criterion. Successively decoding the encoded sequence comprises branching (S108) the decoded sequence into two candidate decoded sequences whenever the threshold check fails.

There is provided a method of obtaining one or more parity symbols (PS) of an encoding of information symbols (IS) according to a linear cyclic code, the method comprising: upon a permutation of information symbols (IS), generating data indicative of parity coefficients of a row of a generator matrix associated with the linear cyclic code, computing, for each given parity coefficient, a first data in accordance with, at least, the given parity coefficient and the first IS; updating, by the processing circuitry, for each given parity coefficient of the one or more parity coefficients, the first data, in accordance with, at least, the given parity coefficient and the respective IS; and upon meeting a parity completion criterion for a given parity coefficient, deriving a parity symbol from the respective first data, thereby obtaining the one or more parity symbols of the codeword of the linear cyclic code.

A sequence detector is provided for detecting symbol values corresponding to a sequence of input samples obtained from a transmission channel. The sequence detector comprises a branch metric unit (BMU), a path metric unit (PMU) and a survivor memory unit. The branch metric unit calculates branch metrics for respective possible transitions between states of a trellis. The path metric unit accumulates branch metrics provided by the branch metric unit in order to establish path metrics. The survivor memory unit selects a survivor path based on the path metrics and outputs a survivor sequence of the detected symbols corresponding to the survivor path. The sequence detector is configured such that the synchronization length is different than the survivor path memory length.

An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z.sub.1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.

Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

A sequence detector is provided for detecting symbol values corresponding to a sequence of input samples obtained from a transmission channel. The sequence detector comprises a branch metric unit (BMU), a path metric unit (PMU) and a survivor memory unit. The branch metric unit calculates branch metrics for respective possible transitions between states of a trellis. The path metric unit accumulates branch metrics provided by the branch metric unit in order to establish path metrics. The survivor memory unit selects a survivor path based on the path metrics and outputs a survivor sequence of the detected symbols corresponding to the survivor path. The sequence detector is configured such that the synchronization length is different than the survivor path memory length.

There is provided a decoder for decoding a data signal received through a transmission channel in a communication system, the decoder (310) comprising a symbol estimation unit (311) configured to determine estimated symbols representative of the transmitted symbols carried by the received signal, the estimated symbols being determined from nodes of a decoding tree based on a weight metric associated with each of the node. The decoder further comprises a termination alarm monitoring unit (312) for monitoring a termination alarm depending on the current decoding computation complexity, the termination alarm being associated with a metric parameter, the symbol estimation unit being configured to reduce the weight metric of each node of the decoding tree by a quantity corresponding to a function of the metric parameter associated with the termination alarm, in response to the triggering of the termination alarm.