An error correction method includes performing a first error correction operation, the first error correction operation including performing a syndrome check operation by calculating a syndrome matrix corresponding to a codeword based on a parity check matrix, performing a decoding operation for the codeword according to a result of the syndrome check operation, and iterating the decoding operation until the syndrome check operation is passed for a codeword acquired as the decoding operation is performed or an iteration count of the decoding operation reaches a threshold count; accumulating syndrome matrixes, which are calculated as the decoding operation is iterated, to an accumulation matrix; and performing a second error correction operation for a last codeword acquired through the iterating of the decoding operation for the codeword, based on the accumulation matrix, when the iteration count reaches the threshold count.

Multi-dimensional parity checker (MDPC) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the MDPC system includes a control register and a parity checker. The parity checker receives data segments accessed from the data region. The parity checker generates and accumulates multi-dimensional parity bits for the data segments and subsequently compares accumulated bits to expected multi-dimensional parity bits to generate multi-dimensional error syndrome bits representing identified comparison errors. The parity checker also determines a syndrome state based upon the multi-dimensional syndrome bits and stores the syndrome state within the control register. The parity checker operates in different modes based upon different values stored in an operational mode field of the control register. The parity checker can operate in a real-time error correction mode to correct errors within the data region from subsequent random accesses by components within the integrated circuit.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.

Described is a decoder suitable for use with any communication or storage system. The described decoder has a modular decoder hardware architecture capable of implementing a noise guessing process and due to its dependency only on noise, the decoder design is independent of any encoder, thus making it a universal decoder. Hence, the decoder architecture described herein is agnostic to any coding scheme.

There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.

A method of telecommunications includes the steps of receiving an encoded block having a plurality of values, dividing the received encoded block into a plurality of received segments, each received segment comprising at least two of the values, decoding each received segment by providing, for each received segment, a plurality of estimated encoded sequences, each estimated encoded sequence comprising at least two data units, merging estimated encoded sequences for consecutive segments to provide a plurality of candidate sequences, and selecting one of the plurality of candidate sequences by performing a closest fit calculation between the received encoded data block and each of the candidate sequences. The method is suitable for use in software-defined radios.

The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

A decoding method includes: decoding first to-be-decoded information based on a first decoder to obtain a first decoding result that includes first soft information or a first hard output; and correcting the first decoding result based on a first correction model to obtain a corrected first decoding result of the first to-be-decoded information. The first correction model is obtained through training based on training data that includes a training decoding result and a corrected training decoding result. The training decoding result is a decoding result obtained after the first decoder decodes training to-be-decoded information, and the corrected training decoding result is a corrected decoding result corresponding to the training decoding result. In this way, after a decoder performs decoding, a decoding result can be corrected based on a correction model.