Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.

The present application concerns an iterative bit-flipping decoding method using symbol or bit reliabilities, which is a variation of GRAND decoding and is denoted by ordered reliability bits GRAND (ORBGRAND). It comprises receiving a plurality of demodulated symbols from a noisy transmission channel; and receiving for the plurality of demodulated symbols, information indicating a ranked order of reliability of at least the most unreliable information contained within the plurality of demodulated symbols. A sequence of putative noise patterns from a most likely pattern of noise affecting the plurality of symbols through one or more successively less likely noise patterns is provided. Responsive to the information contained within the plurality of symbols not corresponding with an element of a code-book comprising a set of valid codewords, a first in the sequence of putative noise patterns is used to invert the most unreliable information of the information contained within the plurality of symbols to obtain a potential codeword, and responsive to the potential codeword not corresponding with an element of the code-book, repeatedly: a next likely noise pattern from the sequence of putative noise patterns is applied to invert a noise effect on the received plurality of demodulated symbols to provide a potential codeword, each successive noise pattern indicating an inversion of information for one or more demodulated symbols for a next more reliable combination of information contained within the plurality of symbols, until the potential codeword corresponds with an element of the code-book.

Disclosed are a method and an apparatus for high-speed decoding of a linear code on the basis of a soft decision. The method for high-speed decoding of a linear code on the basis of a soft decision may comprise the steps of: obtaining an alignment signal by aligning received signals in order of magnitude; obtaining a hard decision signal by making a hard decision on the alignment signal; obtaining a higher-level signal corresponding to most reliable bases (MRB) from the hard decision signal; obtaining a permuted and corrected codeword candidate by using an error vector according to a current order and the higher signal; calculating a cost for the current order by using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost and the minimum cost; and determining a predefined high-speed condition.

According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.

There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.

The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

Systems and methods for correcting corrupted network packets are provided. An example method includes receiving a network packet via a communication channel. The network packet includes a payload and a Cyclic Redundancy Check (CRC) associated with the payload. The method continues with calculating a reference CRC based on the received payload and determining, based on the reference CRC and the received CRC, whether the network packet is corrupted. Based on the determination that the network packet is corrupted, the method continues with selecting a predetermined number of positions of bits in the payload of the network packet, precalculating a set of additional CRCs, and determining, based on the reference CRC and the set of additional CRCs, a combination of bit flips at the predetermined number of positions. The method also includes modifying the payload according to the combination of bit flips at the predetermined number of positions.

Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.

A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

The system and method described provide correction of modulation symbol errors which may occur during audio pairing of computing devices. The transmission between the computing devices comprises a six modulation symbol (24 bit) token containing transaction information and a two check symbol (8 bit) cyclic redundancy check (“CRC”). Error probabilities of symbols are be used to identify probable symbol error locations and the number of errors contained in the received transmission during the symbol decoding process. If there is a single modulation symbol error, the 16 possible combinations of bit values are cycled through until one combination passes the CRC check. If there are two modulation symbol errors, the 256 possible combinations of bit values are cycled through until two combinations pass the CRC check.